The realization of VHDL UART

Today, nothing is boring, write two blog to kill time ...

This blog first introduces the basic principles of the UART, and then post my code.

The UART is a serial data transmission format that sends and receives only one signal line for each use. It is often used in low-rate signal transmission, but it is necessary to change the transmission mode at high-speed data transmission, such as using Mac ETHERNET.

To get to the point, first I UART the format of the data sent/received is: A starting bit (0), 8 data bits, a stop bit (1). When there is no data transfer on the TX/RX, the signal line is 1.

The program has 3 sub-modules, which are sent, received and baud rate generated.

Paste the following code:

library IEEE, use IEEE.
Std_logic_1164.all; Use IEEE. Std_logic_arith.
All; Use IEEE. std_logic_unsigned.
All;
	       Entity baud is---9600*16 Port (Clk:in std_logic;
Bclk:out std_logic);
End baud;
Architecture behavioral of baud is begin process (CLK) variable Cnt:integer; Begin if Rising_edge (CLK) Then if cnt>=325 then cnt:=0;                        bclk<= ' 1 '; --Set the crossover factor 305ori else cnt:=cnt+1;
	 bclk<= ' 0 ';
  End If;
End If;
End process;
End behavioral; 

Library IEEE;
Use IEEE. Std_logic_1164.all;
Use IEEE. Std_logic_arith. All;
Use IEEE. std_logic_unsigned. All;
Entity BAUD2 is                 ---9600
    Port (clk:in  std_logic;
	       Bclk:out std_logic);
End Baud2;
Architecture behavioral of BAUD2 is
begin
Process (CLK)
variable cnt:integer:=0;
Begin                           
  If Rising_edge (CLK) then
     if cnt>=5208 then cnt:=0; bclk<= ' 1 ';                        --Set the crossover coefficient 206
	 else cnt:=cnt+1; bclk<= ' 0 ';
	 End If;
  End If;
End process;
End behavioral;

Send Module

Library IEEE;
Use IEEE. Std_logic_1164.all;
Use IEEE. Std_logic_arith. All;
Use IEEE. std_logic_unsigned. All;

Entity TX2 is
	port (
		baud:in  std_logic;
		EN   : In  std_logic;
		BUF  : In  std_logic_vector (7 Downto 0);
		TXD  : Out std_logic
	);
End TX2;

Architecture BV of TX2 is
begin

	Process (BAUD)
   	variable cnt:integer:= 0;
	Begin
-		if EN = ' 1 ' then 
		  if Rising_edge (BAUD) then case
			  CNT was when
			  	  0 = txd<= ' 0 '; cnt:=cn t+1;
				  When 9 = txd<= ' 1 '; cnt:=0;
				  When others = TXD <=buf (cnt-1); cnt:=cnt+1;   
			  End case;
		  End If;
	--	Else
	--		TXD <= ' 1 ';

--		End If;
		
	End process;
	
End architecture;

Receiving module

Library IEEE; Use IEEE.
Std_logic_1164.all; Use IEEE. Std_logic_arith.
All; Use IEEE. std_logic_unsigned.
All;	         
    Entity RX is generic (framlenr:integer:=8);                        
	     Port (Bclkr,resetr,rxdr:in std_logic;
		 R_ready:out std_logic;
Rbuf:out Std_logic_vector (7 Downto 0));
End RX;         
Architecture Behavioral of RX is type states is (R_start,r_center,r_wait,r_sample,r_stop);
Signal State:states:=r_start;
Signal rxd_sync:std_logic;
  Begin Pro1:process (RXDR) BEGIN if rxdr= ' 0 ' then rxd_sync<= ' 0 ';
  else rxd_sync<= ' 1 ';
End If;

End process;                     
Pro2:process (bclkr,resetr,rxd_sync) variable count:std_logic_vector (3 Downto 0);
Variable rcnt:integer:=0;
Variable rbufs:std_logic_vector (7 Downto 0); Begin if resetr= ' 1 ' then state<=r_start;                
  count:= "0000"; elsif Rising_edge (BCLKR) then case state was when r_start=> if Rxd_sync= ' 0 ' then State<=r_Center r_ready<= ' 0 ';
			rcnt:=0; else state<=r_start;
			r_ready<= ' 0 ';                              
End If;  When r_center=> if rxd_sync= ' 0 ' then if count= "0100" then state<=r_wait;
count:= "0000"; else count:=count+1;
state<=r_center;
			End If;
			else state<=r_start;                            
End If;
			    When r_wait=> if count>= "1110" then if Rcnt=framlenr then state<=r_stop;
			    else state<=r_sample;
			End If;                    
		    count:= "0000"; else count:=count+1;
			state<=r_wait;
End If; When R_sample=>rbufs (rcnt): =rxd_sync;
                                                   
       rcnt:=rcnt+1;state<=r_wait; When r_stop=>r_ready<= ' 1 '; rbuf<=rbufs;  
       state<=r_start;
     When others=>state<=r_start;
  End case;
End If;
End process;
 End behavioral;

It can be seen that the launch part is easy, but the implementation of reception is more complex.