With the price of memory down, many netizens for their own machine configured with high capacity memory, increasing the memory capacity can not only improve the reading and writing speed, but also improve the performance of the system; However, a single large memory on some motherboards (a longer motherboard) is either unrecognized or error-aware (capacity-recognition error). What is the cause of this? First of all, we know some memory knowledge, I believe netizens will find the answer in it.
The logical bank of a memory chip
We know that the 32MB/64MB/128MB used on the motherboard are made up of several memory chips welded on the 4 or 6-layer circuit board, so first we must have a clear understanding of the internal structure of the memory chip, see the following figure:
On the inside of the chip, the memory data is written in bits (bit) in a large matrix, each cell we call the cell, as long as the specified row, and then specify a column (columns), you can accurately locate a cell, which is the basic principle of memory chip addressing. This array is called the Bank of the memory chip, also known as the Logical Bank (Logical Bank). Because of the process, the array can not do too much, so the general memory chip is divided into several arrays of memory capacity to create, that is, there are many logical bank memory chips, as the chip capacity is increasing, the number of logical bank is also increasing, At present, the chips from 32MB to 1GB are basically 4, and only the early 16Mbit and 32Mbit chips used 2 logical BANK designs, such as Samsung's two kinds of 16MB chips: k4s161622d (512K x 16Bit x 2 BANK) and K4s160822dt (1M x 8Bit x 2 BANK). The chipset itself is designed to operate on only one logical bank during a clock cycle (in fact, the bit width of the chip is the bit width of the logical bank), not the chipset operating on all logical bank in the memory chip. The logical bank's address line is generic, as long as there is another logical bank number to distinguish it (BANK0 to BANK3). But the bit width of the chip determines how much data can be read from it at a time, not all of the cells in the memory chip can be read at once, and the following figure is a schematic diagram of the internal logical bank structure of a 32MB (256Mbit) memory chip, from which you can better understand the structure of the logical bank
As can be seen, the DQ data input/output line is only 8 instead of 32, you can find that 4 bank is time-sharing, at any one time only one bank data can be accessed, 0-3 is their number. Each logical bank has 8M cells (cell), and some vendors (such as Hyundai/Samsung) refer to each logical bank's cell number as the data depth (Depth), each of which consists of 8bit, and the total capacity of a logical Bank is 64Mbit (8mx8bit ), 4 logical Bank is 256Mbit, so the total capacity of this chip is 256Mbit (32MB).
The capacity of memory chips is generally in bit. For example, 32Mbit chip, that is, its capacity is 32Mb (b=bit= bit), attention bit (bit) and byte (byte) difference, this chip conversion into bytes is 4MB (b=byte= byte = 8 bit), the general memory chip manufacturers on the chip is marked capacity, We can know on the chip that the chip has a few logical bank, the bit width of each logical bank, how many cells in each logical bank, such as the current 64MB and 128MB memory chips commonly used 64Mbit chips have the following three kinds of structure form:
①16 meg x 4 (4 Meg x 4 x 4 banks) [16m╳4]
②8 meg x 8 (2 Meg x 8 x 4 banks) [8m╳8]
③4 meg x (1 meg x 4 banks) [4M╳16]
The notation is: the number of cells per logical Bank x logical Bank Quantity x the number of bits per cell (the bit width of the chip). Chip logic Bank bit width The current process level can only do up to 16 bits, so you can see that almost all of the chip logic bank bit width is only possible 4/8/16 one of three. The previous 16Mbit chip basic use of a single chip two logical bank, but to 64Mbit is basically all 4 logical bank design, in the future with the production process level to estimate a single chip 8 or even 16 logical bank appearance is not impossible.
Two. The physical bank of the memory strip
Typically each memory slot on the motherboard is divided into two segments, which is easily inferred from the bank 0/1 DRAM timing option in the VIA Motherboard BIOS setup, which is actually two bank But the bank concept here is different from the bank mentioned in the previous analysis of the internal structure of the chip. To put it simply, the bank is the channel between the memory and the North Bridge chip on the motherboard for exchanging data, now, for example, SDRAM system, the interface between CPU and memory (that is, CPU to DIMM slot) is 64bit, Also means that the CPU will be sent to memory at one time or read 64bit of data from memory, then this is a 64bit data collection is a bank of memory, many manufacturers of product descriptions called the physical Bank (physical bank), At present, most chipsets can only support a single memory containing two physical banks, but for a specific note, many people take it for granted that each DIMM slot uses the number of sides of the memory bar to distinguish between several bank channels, one side (16m,64m) to occupy a single physical bank, and double-sided ( 32m,128m) is required to occupy two physical bank. In fact, the physical bank and surface number is irrelevant, the PCB circuit can be designed double-sided and single-sided, but also the entire chip (16) on one side (at least theoretically is completely possible). Some of the memory strip is a single physical bank, but some double-sided is a physical bank, so can not generalize. Before the uproar of the magnanimous 256MB memory bar is a typical example, although it is double-sided and up to 16 chips, but still a single physical bank. To know exactly how much the actual physical bank is, we have to figure out the logical bank number and the bit width of a single chip and the number of chips on the memory bar. Each chip bit width of the sum of 64 is a single physical bank, if 128 is the double physical bank. The current chipset supports up to 2 physical bank. Therefore, memory manufacturers can not produce more than 2 physical bank.