Well, the lab's embedded project needs to write the device driver, I got the network-driven live, write a fit Sylixos (here boast, this is really a good domestic embedded real-time operating system) MPC8377 of the network card driver, to tell the truth has never touched the writing drive things, Not to mention the complicated NIC driver. So be prepared to look at what others have written, and make a clear idea. To be reasonable, now I really do not even know what the NIC is.
The first day looked at the Sylixos arm2440 of the dm9000 network card driver, the kernel of the Internet protocol stack is LWIP. Probably looked at the whole drive of the frame ... With a general impression, and then consulted the Sylixos engineers a lot of questions.
Because of the accumulation in the embedded system is too little, so I have a lot of embedded concept is really not clear ..... For example, I think that the write network card driver is really write a "network card" driver, the result of the network card composition is what do not know ...
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Ethernet (Ethernet) is a computer LAN networking technology, based on the IEEE 802.3 standard, which specifies the physical layer of wiring, electrical signals and media Access layer protocol content. Ethernet is the most common LAN technology in the current application. It largely replaces other LAN standards, such as Token Ring, FDDI, and Arcnet. After the rapid development of 100M Ethernet at the end of the last century, gigabit Ethernet and even 10G Ethernet are expanding the scope of application under the impetus of international organizations and leading enterprises. Ethernet-based application is a research and development hotspot in a certain period.
The Ethernet interface is essentially the process by which a Mac controls PHY via the Mii bus.
is a schematic diagram of the network port. The network port consists of three parts: CPU, Mac and PHY. The DMA controller is usually part of the CPU and is placed with a dashed line to indicate that the DMA controller may be involved in the network port data transfer.
For the above three parts, and not necessarily are independent of the chip, according to the combination of forms, can be divided into the following types:
1.CPU Integrated Mac and PHY;
2.CPU integrated mac,phy with independent chip;
3.CPU non-integrated Mac with PHY,MAC and PHY with integrated chip;
MPC8377 just belongs to the second kind, the board is ETSEC integrated +8e1111 PHY chip.
is the network port structure diagram using scenario two. A dashed box indicates that the CPU,MAC is integrated in the CPU. The PHY chip is connected to the Mac on the CPU via the Mii interface.
The operation of the network port on the software is usually divided into the following steps:
1. Allocate memory for data sending and receiving;
2. Initialize the MAC register;
3. Initialize the PHY register (via MIIM);
4. Start sending and receiving;
In terms of the OSI seven layer structure, the MAC is at the data link layer, and the PHY belongs to the physical layer.
The 1.MACMAC is the abbreviation for media access control, which is the sub-layer protocol for the medium accesses controls. The protocol is located in the lower half of the data link layer in the OSI Seven layer protocol, and is primarily responsible for controlling and connecting physical media to the physical layer. When the data is sent, the MAC protocol can determine in advance whether the data can be sent, if it can be sent to the data with some control information, and finally the data and control information in the specified format sent to the physical layer, when the data is received, the MAC protocol first to determine the information entered and whether transmission error occurred, If there is no error, the control information is removed and sent to the LLC layer. Ethernet MAC is defined by the IEEE-802.3 Ethernet standard. The 2.MIIMII is a media-independent interface, and "media independence" indicates that any type of PHY device can work correctly without the MAC hardware being redesigned or replaced. Includes two separate channels for transmitters and receivers, respectively. Each channel has its own data, clock, and control signals. The MII data interface requires a total of 12 signals, including:
- Transmit data-txd[3:0]////sent data
- Transmit strobe-tx_en////Send enable
- Transmit clock-tx_clk///10/100m Signal Clock
- Transmit error-tx_er/txd4////transmitter Error
- Receive data-rxd[3:0]///receiving data
- Receive strobe-rx_dv///receiving data valid indication
- Receive clock-rx_clk///receiving signal clock
- Receive error-rx_er/rxd4///receiving data error indication
- Collision indication-col////Conflict Detection
- Carrier sense-crs////Carrier Detection
- Management data clock-mdc////Management Configuration Interface
- Management data Input/output-mdio////Management Configuration Interface IO
Mii transmits data in 4bit, or half-byte, in two directions, with a clock rate of 25MHz and a working speed of up to 100mb/s. The Mii management interface is a two-signal interface, one is a clock signal and the other is a data signal. Through the management interface, the upper layer can monitor and control phy. The Mii interface transmits the control of all data and data on the network, while the MAC's determination of the working state of the PHY and the control of the PHY is done using the SMI (Serial Management Interface) interface through the read/write PHY registers. Part of the register in PHY is defined by IEEE, so that PHY reflects its current state into the register, and the Mac continuously reads the state register of PHY through the SMI bus to know the current PHY state, such as connection speed, duplex capability, etc. Of course, you can also set the PHY register through the SMI to achieve control purposes, such as the open shutdown of the flow control, self-negotiation mode or mandatory mode. Both the physical connection of the Mii bus and the SMI bus or PHY's status register and Control register are IEEE-compliant, so the Mac and PHY of different companies can work in harmony. Of course, in order to match the different company's PHY's own certain function, the driver needs to make the corresponding modification. RMII (Reduced media independant Interface) simplifies the media stand-alone interface and is one of the standard Ethernet interfaces with fewer I/O transmissions than Mii. Basic differences about the/mii/gmill of Rmii mouth:
The Rmii port uses 2 wires to transmit the data.
The MII port uses 4 wires to transmit data.
Gmii is using 8 wires to transmit data.
Mii/rmii is just an interface, for 10M wire speed, the Mii clock is 2.5m,rmii 5M; for 100M wire speed, the Mii clock is 25m,rmii 50M. Mii/rmii is used for transmission of Ethernet packets, in the Mii/rmii interface is 4/2bit, in the Ethernet PHY need to do string and conversion, codec, etc. to be transmitted on twisted pair and fiber, its frame format follows IEEE 802.3 (10M)/ieee 802.3u (100M) /ieee 802.1q (VLAN). The format of the Ethernet frame is:
Leader + start bit + Destination MAC address + source MAC address + type/length + data +padding (optional) +32BITCRC
If there is a VLAN, then add a 2-byte VLAN tag after the type/length, where 12bit represents the VLAN ID, and 4bit represents the priority of the data! The 3.PHYPHY is a physical interface transceiver that implements the physical layer. Includes MII/GMII (media Independent interface) sub-layer, PCS (physically encoded sub-layer), PMA (physical media attached) sub-layer, PMD (physical medium dependent) child layer, MDI child layer.
The 100BaseTX uses 4B/5B encoding. PHY when sending data, received MAC data (for PHY, there is no frame concept, for it, is data regardless of address, data or CRC), every 4bit to increase the error code of 1bit, and then the parallel data into serial stream data, and then according to the physical layer coding rules to encode data , and then into an analog signal to send the data out. The process in which data is collected is reverse. One important function of PHY is to implement some of the functions of CSMA/CD. It can detect whether there is data on the network in the transmission, if there is data in the transmission of the wait, once the network is detected idle, and then wait for a random time to send data out. If two happen to send the data at the same time, that will inevitably cause a conflict, when the conflict detection agencies can detect the conflict, and then wait for a random time to resend the data. This random time is very fastidious, not a constant, the random time calculated at different times are different, and there are multiple algorithms to cope with the probability of a very low occurrence of the second collision between the two hosts. The communication rate is negotiated by both parties, and the result of the negotiation is the maximum speed and the best duplex mode that can be supported simultaneously in both devices. This technique is called auto negotiation or Nway. The isolation transformer sends the differential signal from the PHY with a differential-mode coupled coil-coupled filter to enhance the signal and is coupled to the other end of the connection cable by the conversion of the electromagnetic field. RJ-45 1, 2 is the transmission of data, 3, 6 is to receive data. The new PHY supports the Auto Mdi-x feature (also requires isolation transformer support). It can realize the function of transmitting signal line on the 1 and 2 of the RJ-45 interface and receiving signal line on 3 and 6 to exchange automatically with each other.
The NIC works on the last two layers of the OSI, the physical layer and the data link layer, and the physical layer defines the electrical and optical signals, line States, clock benchmarks, data encoding, and circuitry needed for data transmission and reception, and provides a standard interface to the data link layer device. The physical layer of the chip is called PHY. The data link layer provides the functions of addressing mechanism, data frame construction, data error checking, Transmission control, and providing standard data interface to the network layer. The chip of the data link layer in the Ethernet card is called the Mac controller. Many of these two parts of the NIC are done together. Their relationship is the PCI bus connected to the Mac bus, Mac connected to the Phy,phy network cable (of course, is not directly connected, there is a pressure swing device).
Thus, the MAC and PHY, one is the data link layer, the other is the physical layer, both transmit data through the MII. yuan:52174259
The relationship and difference between MAC, MII and PHY
