Compare | Experience recently to the collation of a CPU information, should be more comprehensive it.
Almost all X86 CPUs now have built-in CPUID instructions to identify the authenticity, and some CPU manufacturers such as Amd,via also have a richer extension cpuid instructions built in, more convenient.
Below we use Delphi to implement a CPU detection software.
The CPUID is invoked as follows:
Asm
Push EAX
Push EBX
Push ECX
Push edx
MOV eax,x
//******************************************************
CPUID instruction, because the Delphi Assembler compiler does not have this instruction built in,
Therefore, the machine language code of the instruction is $0f, $A and second implementation
//******************************************************
DB $0f, $A 2
Pop edx
Pop ecx
Pop ebx
Pop eax
End
The parameter of the CPUID instruction is Eax,mov eax,x The sentence is to assign X to EAX.
The returned parameters are stored in the Eax,ebx,ecx,edx.
We can write a function:
Type
Tcpuidresult = Record
Eax:dword;
Ebx:dword;
Ecx:dword;
Edx:dword;
End
......
function CPUID (Eax:dword): Tcpuidresult;
Asm
Push EAX
Push EBX
Push ECX
Push edx
MOV eax,eax
//******************************************************
CPUID instruction, because the Delphi Assembler compiler does not have this instruction built in,
Therefore, the machine language code of the instruction is $0f, $A and second implementation
//******************************************************
DB $0f, $A 2
MOV result.eax,eax
MOV result.ebx,ebx
MOV result.ecx,ecx
MOV Result.edx,edx
Pop edx
Pop ecx
Pop ebx
Pop eax
End
CPUID parameter and return value list:
eax= 0000_0000h
Input eax=0000_0000h Gets the maximum value supported by the CPUID directive and the name string of the manufacturer
The output eax=xxxx_xxxxh gets the maximum value supported by the CPUID instruction #1
EBX-EDX-ECX manufacturer's name string #2
Genuineintel Intel processors
UMC UMC UMC UMC processor
AUTHENTICAMD AMD Processors
Cyrixinstead Cyrix Processor
Nexgendriven NexGen Processor
Centaurhauls Centaur Processor
Riseriserise Rise Technology Processor
GenuineTMx86 Transmeta Processor
Geode by NSC National Semiconductor processor
Description description
#1 pre-b0 Step Intel P5 processor returns EAX=0000_05XXH.
#2 pre-b0 Step Intel P5 processor cannot return the vendor string
eax= 0000_0001h
Input eax=0000_0001h get processor type/family/model/stepping and face identification
Output EAX=XXXX_XXXXH Processor type/family/model/stepping
Extended family extended family is bits 27..20.
00h Intel P4
01h Intel Itanium 2 (IA-64)
Extended model extended model is bits 19..16.
Type type is bit 13 and bit 12.
11b Retention
10b Second processor
01B Overdrive Processor
00B First Processor
Family family is bits 11..8.
4 Most 80486s
AMD 5x86
Cyrix 5x86
5 Intel P5, p54c, p55c, p24t
NexGen Nx586
Cyrix M1
AMD K5, K6
Centaur C6, C2, C3
Rise mP6
Transmeta Crusoe tm3x00 and tm5x00
6 Intel P6, P2, P3
AMD K7
Cyrix M2, VIA Cyrix III
7 Intel Itanium (IA-64)
F if that's the value, look at extended family.
Model model is bits 7..4.
Intel F If that's the value, look at extended model.
Intel 80486 0 I80486dx-25/33
1 i80486dx-50
2 I80486SX
3 I80486DX2
4 I80486SL
5 I80486SX2
7 I80486DX2WB
8 I80486DX4
9 I80486DX4WB
UMC 80486 1 u5d
2 u5s
AMD 80486 3 80486dx2
7 80486DX2WB
8 80486DX4
9 80486DX4WB
E 5x86
F 5X86WB
Cyrix 5x86 9 5x86
Cyrix MediaGX 4 GX, GXm
Intel P5-core 0 P5 A-step
1 P5
2 p54c
3 P24T Overdrive
4 p55c
7 p54c
8 p55c (0.25μm)
NexGen Nx586 0 Nx586 or NX586FPU (only later ones)
Cyrix M1 2 6x86
Cyrix M2 0 6x86mx
VIA Cyrix III 5 Cyrix M2 Core
6 WinChip c5a Core
7 WinChip c5b Core (if stepping = 0..7)
7 WinChip c5c Core (if stepping = 8..F)
8 WinChip C5c-t Core (if stepping = 0..7)
AMD K5 0 SSA5 (PR75, PR90, PR100)
1 5k86 (PR120, PR133)
2 5k86 (PR166)
3 5k86 (PR200)
AMD K6 6 K6 (0.30μm)
7 K6 (0.25μm)
8 K6-2
9 K6-III
D k6-2+ or k6-iii+ (0.18μm)
Centaur 4 C6
8 C2
9 C3
Rise 0 mP6 (0.25μm)
2 mP6 (0.18μm)
Transmeta 4 Crusoe tm3x00 and tm5x00
Intel P6-core 0 P6 A-step
1 P6
3 P2 (0.28μm)
5 P2 (0.25μm)
6 P2 with On-die L2 cache
7 P3 (0.25μm)
8 P3 (0.18μm)
With 256 KB On-die L2 cache
A P3 (0.18μm)
With 1 or 2 MB on-die L2 Cache
B P3 (0.13μm)
With 256 or On-die KB L2 cache
