The second stage of Self-writing processor (1) -- Design Process of programmable logical devices and PLD Circuits

I will upload my new book "self-writing processor" (not published yet). Today is the fifth article. I try to write this article every Thursday.

 

Based on the introduction in the previous chapter, you should know that the CPU has some basic circuits, such as decoding circuit, calculation circuit, control circuit, and some registers. How can these circuits be implemented? Of course, it can be achieved through a lot of discrete components. In fact, in 2008, game developers in California, Steve Chamberlin, created an 8-bit CPU, which took 18 months and spent $1000, A total of 1253 cables were used, as shown in Figure 2-1. Steve Chamberlin gave it a very appropriate name-bmow (big mess of wires ).

 

 

Another friend named Bill buzbee also made a CPU with over 200 pieces of 74 series TTL integrated circuit.

The above events only prove the feasibility of using discrete components to implement the CPU, but it is not a good way to implement the CPU. This book uses the "code + FPGA" method to implement the CPU, in this chapter, we will explain the principles and introduce the use of the programming language.

2.1 Overview of programmable logical devices

FPGA is a programmable logic device. PLD was a new type of device developed in the 1970s S. Its application and development not only simplifies circuit design, reduces development costs, but also improves system reliability, it has brought revolutionary changes to the design method of digital systems. Up to now, there have been a variety of process, different principles of PLD, as shown below.

• PLA (Programmable Logic Array) Programmable Logic Array
• Pal (Programmable Array Logic) programmable Array Logic
• Gal (Generic Array Logic) General Array Logic
• Prom (programmable read-only memory) programmable read-only memory
• EPLD (Erasable Programmable Logic Device) Erasable Programmable Logic Device
• Complex Programmable Logic Device (CPLD)
• Field Programmable Gate Array

Based on different internal structures, PLD devices can be divided into the following two categories.

1. PLD Device Based on Product-Term Structure

Any function of a logic circuit can be converted into a "and" or "expression, which is implemented using a" and gate-or gate "circuit. Any time series circuit can be composed of a combination circuit and a storage component (trigger). Therefore, in principle, any digital logic circuit can be implemented by adding a trigger structure to an array or array. The primary structure of the PLD Device Based on the product item structure is the connection with or array, which achieves any logical function through flexible configuration. The basic structure is 2-2.

A product-based PLD Device consists of an input buffer circuit, an array, or an array, and an output buffer circuit. "With arrays" and "or arrays" are the main bodies used to implement various logical functions and logical functions. The input buffer circuit is used to generate the original and inverse variables of the input signal, and enhance the driving capability of the input signal. The output buffer circuit is mainly used to process the signal to be output. It can output both the pure combination logic signal and the time series logic signal.

Prom, PLA, pal, gal, EPLD, and most CPLD devices use product-term (PLD) structures, which are based on the internal and or Array Logic, these devices are mostly made using the eeprom or flash process. configuration data is not lost after power loss, and the device size is generally less than 5000.

2. PLD Device Based on the structure of the query table (LUT: look-up table)

The scale of the and or array-based PLD Device is not easy to be very large, so the designer developed another programmable logic device, that is, to find the table structure. It is similar to Rom. Its physical structure is based on static memory (SRAM: static RAM) and data selector (MUX), and functions are implemented through Table query. The function value is placed in the SRAM, and the address line of the SRAM is the input variable. Different inputs use MUX to find the corresponding function value and output it. The logical functions of N input items can be implemented by a 2n-bit SRAM.

Figure 2-3 uses a two-input query table to implement two input or gate operations. 2. The input search table has four storage units to store the four values in the truth table. The input variables A and B are used as the address selection ends for the three multi-path selector in the search table, based on the combination of A and B values, select one of the four storage units as the output of the query table, which implements the logic function of two inputs or doors.

The table structure query function is very powerful. You can use logical functions to search for any N input variables for N input tables. Theoretically, as long as the input signal line can be increased and the memory capacity can be expanded, any input variable function can be implemented by using a search table. However, in practical applications, the table search scale is limited by technical and cost factors. Each time an input variable is added, the capacity of the queried table SRAM is doubled. The relationship between the capacity of the SRAM and the number of input variables N is 2n times. 8. The query table for input variables requires a-B SRAM capacity, while the query table for 16 input variables requires a 64-kb SRAM capacity, which is intolerable. In fact, there are generally no more than five input variables in the FPGA device lookup table. Logical Functions with more than five input variables can be implemented by multiple Lookup tables through combination or cascade.

Most FPGA Devices are implemented based on the SRAM lookup table structure. It features high integration (supporting more than one million logic gates) and strong logic functions. It can implement large-scale Digital System Design and complex algorithm operations. However, configuration data will be lost after power loss, A plug-in is required to store configuration data to form an independent operating system. In FPGA, more logical functional blocks are generally integrated, such as memory blocks, DSP Blocks, hardware multiplier, and digital phase-locked loops, it is used to meet the needs of digital signal processing, digital communication and other applications.

The practical version of openmips processor that is finally implemented in this book will be downloaded to FPGA for running, using the ep2c35 series FPGA of Altera, which has 33216 le (logic element ), each le consists of a 4-input lookup table and a programmable register.

2.2 PLD-based digital system design process

PLD is not only a technological innovation, but also a conceptual innovation and a design process innovation. The PLD-based digital system design process is shown in 2-4. This section describes each stage of the process.

2.2.1 design input

Design input refers to the process of expressing the circuit designed by the designer in some form of developing software requirements and inputting it into the corresponding software. There are multiple ways to design the input, the most commonly used is the schematic and HDL text.

1. Schematic Input

The schematic diagram (schematic) is a graphical expression that describes the design using component symbols and links. Schematic input is intuitive to users, especially for presentation of hierarchies and modular structures. It is suitable for describing the connection and interface relationships, while the logical description function is cumbersome. It requires design tools to provide necessary component libraries or logical macro units. If the input is a complex logic or a model does not exist in the component library, it is often inconvenient to use the schematic input method. In addition, the schematic design is reusable and portable.

Figure 2-5 shows a circuit using a selector selected by the schematic input. There are three inputs: A0, A1, and S. One outputs Y. When S is 1, the value of Y is equal to the value of A1. When S is 0, the value of Y is equal to the value of A0.

2. HDL text input

Hardware Description Language (HDL: Hardware Description Language) is a language used to describe and design circuits in the form of text. Designers can use the HDL language to describe their own designs, and then use the corresponding tools for synthesis, into a certain target file, and finally download to the PLD Device to implement a specific circuit. Currently, commonly used HDL algorithms include VHDL and Tilde.

Each of the advantages of VHDL and OpenGL can be applied to logic design at the algorithm level (algorithm levels), register transfer level (RTL), gate level (Gate levels), and other levels, you can also perform simulation and timing analysis. Due to the standardization of the HDL language, it is easy to transplant the design to chips of different manufacturers, and the signal parameters are also easy to change and modify. In addition, the design by using HDL also has process independence, so that designers do not have to consider the specific details of the door level and process implementation in the functional design and logic verification stages, according to the requirements of the system design, different constraints can be applied to design the actual circuit. The following is the code that uses the two selector that is implemented by using OpenGL.

module mux2(a0, a1, s, y);      input  s, a0, a1;      output y;      assign y = s ? a1 : a0;endmodule

 

This book uses OpenGL to implement the openmips processor.

2.2.2 Integration

Synthesis is a process of automatically converting design descriptions at a higher level of abstraction into design descriptions at a lower level. There are several comprehensive forms.

• Converts algorithm representation and behavior description to register transfer level (RTL), that is, from behavior description to structure description.
• Converting RTL-level descriptions to logic-level descriptions is called logical synthesis.
• The logic gate representation is converted to the configuration Network table representation of the PLD Device. With the configuration Network table, the system implementation based on the PLD Device can be completed.

The synthesizer is a software tool that can automatically implement the preceding conversion, it can compile the circuit diagram or the circuit expressed and described by the HDL language into a circuit network Table consisting of logical units such as the OR array, Ram, trigger, and register.

2.2.3 layout and wiring

Layout cabling can be understood as the process of ing the integrated circuit network table to a specific target PLD Device and generating the final downloadable file. The layout and wiring map the integrated circuit network table to a specific target PLD Device, and divide the entire design into multiple logical small blocks suitable for the implementation of logical resources in the PLD Device, make a choice or compromise between the speed and the area according to the user's settings. The layout is to place the split logical blocks to the specific locations of the logical resources inside the PLD Device and make them easy to connect; wiring uses the wiring resources of the PLD Device to connect functional blocks and feedback signals.

After the layout and wiring are completed, the following important files are generated.

1. Report on chip resource consumption.

2. A delayed network table structure is generated to facilitate accurate timing simulation and accurately predict the actual performance of future chips.

3. device programming files, such as JEDEC and POF files for CPLD programming, and files in SOF, jam, and bit formats for FPGA configuration.

2.2.4 download

The process of placing the device programming files generated during layout and wiring into PLD is called download. Generally, the download of a CPLD device is called programming, and the download of an FPGA device is called configuration ). After the download, the internal and or gate (for FPGA, the query table) of the PLD will change according to the requirements of the Programming file, thus implementing the designed circuit.

2.2.5 Simulation

Figure 2-4 shows a simulation link. Simulation, also known as simulation, tests the functions of the designed circuit. You can simulate the entire system and each module during the design process, that is, verify whether the function is correct with software on the computer and whether the timing coordination of each part is accurate. If any problem occurs, you can modify it at any time to avoid logical errors. A larger design requires simulation.

Simulation includes functional simulation and timing simulation. Simulation without considering factors such as signal delay is called functional simulation, also called pre-simulation; time series simulation is also called post-simulation, it is a simulation of latency after selecting a specific device and completing the layout and wiring. Because the internal latency of different devices is different, different layout and wiring schemes also affect the latency. Therefore, in the design and implementation process, timing simulation is performed on the network and logical block to analyze the timing relationship, it is necessary to estimate the design performance.

The teaching version of openmips processor in this book mainly uses simulation to verify whether it is implemented correctly. Only the practical version of openmips is configured in a specific FPGA chip.

2.2.6 tool Introduction

Tools are supported at each stage of the PLD-based digital system design process. Some tools are integrated to complete all stages of the design process, some tools are designed for a specific design stage. This book uses the following tools to design and implement the openmips processor.

• Design input tool: ultraedit
• Simulation tool: Modelsim
• Integrated Tool: QuartusII

Because openmips of the practical version is downloaded to the FPGA chip of Altera, the integrated tool uses the quartuⅱ of Altera. Generally, it is better to select the tool provided by the target PLD chip manufacturer because the vendor's tool will optimize the design based on the technical characteristics of the device, this improves resource utilization, reduces power consumption, and improves performance.

 

Not complete to be continued!