The structure of the router

The architecture of the router

From the view of architecture, routers can be divided into first generation single-bus single CPU router, second generation single bus CPU router, third generation single bus symmetric multi CPU structure router, fourth generation multi-bus multi-CPU router, fifth generation shared memory structure router, The sixth generation of cross switch architecture routers and routers based on cluster system are many kinds.

The composition of the router

Routers have four elements: input ports, output ports, switching switches, and routing processors.

The input port is the physical link and the import of the input package. Ports are usually provided by a wire card, and a single line card typically supports 4, 8, or 16 ports, and one input port has many features. The first feature is the encapsulation and encapsulation of the data link layer. The second function is to find the destination address of the input package in the forwarding to determine the destination port (known as routing lookup), which can be implemented using general hardware, or by embedding a microprocessor on each line card. Third, in order to provide QoS (quality of service), the port is divided into several predefined service levels for the packets received. Finally, ports may need to run data link-level protocols such as SLIP (Serial Line Internetwork Protocol) and PPP (Point-to-Point Protocol) or network-level protocols such as PPTP (Point-to-Point Tunneling Protocol). Once the routing lookup is complete, the packet must be sent to its output port with a switching switch. If the router is an input-side plus queue, there are several inputs that share the same switch. The final function of this input port is to participate in the arbitration agreement for public resources such as switching switches.

Switching switches can be implemented using a variety of different techniques. The switch technology that has been used up to now is bus, crossover switch and shared memory. The simplest switch uses a single bus to connect all the input and output ports, and the disadvantage of the bus switch is that its exchange capacity is limited by the capacity of the bus and the additional overhead of quorum for the shared bus. A crossover switch provides multiple data paths through a switch, and a crossover switch with a NXN intersection can be considered to have a 2N bus. If a crossover is closed, data on the input bus is available on the output bus, otherwise it is unavailable. The closure and opening of intersections are controlled by the scheduler, so the scheduler restricts the speed of switching. In a shared memory router, incoming packets are stored in a shared memory, swapping only the packets ' pointers, which increases the exchange capacity, but the speed of the switch is limited by the memory's access speed. Although memory capacity can be doubled every 18 months, memory access time is reduced by only 5% a year, which is an inherent limitation of shared memory switching switches.

The output port is stored on the packet before it is sent to the output link, and a complex scheduling algorithm can be implemented to support the priority requirements. As with the input port, the output port also supports the package and encapsulation of the data link layer, as well as many of the more advanced protocols.

The routing processor calculates the routing protocol and runs the software that configures and manages the router. At the same time, it also handles those packets whose destination address is not in the online card forwarding publication.