TI DM6437 EDMA3 Use summary

1. Overview

The basic use of the EDMA3 controller is to transfer data independently from the CPU in bulk.

Typical usage:

A: Service external memory (e.g. DDR)

B: Memory within the service chip (e.g., L2 SRAM)

C: Service peripherals, such as: Serial port

Main purpose: Reduce the data transmission task of DSP.

The EDMA3 controller consists of 2 main modules:

The EDMA3 Channel controller (EDMA3CC) acts as the user interface for the EDMA3 controller, EDMA3CC includes: Parameter RAM (PaRAM) channel control Register, interrupt control register. EDMA3CC is responsible for the priority management of the software request or peripheral events and publishes the transfer request (TRs) to the transfer controller.

The EDMA3 transfer controller (EDMA3TC), which is attached to the EDMA3 channel controller, is responsible for data transmission, EDMA3TC to the source and destination address of the programming transmission to publish read-write requests.

2: Structure

2.1 EDMA3 Channel Controller (EDMA3CC)

Figure 2:EDMA3 Transfer Controller block diagram

2.3 EDMA Transmission Type

EDMA3 transmissions are always based on three-dimensional, and these 3 dimensions are defined as:

1th dimension or Array (a): The 1th dimension of a transport is made up of acnt contiguous bytes.

2nd dimension or FRAME (B): The 2nd dimension of a transport is an array of acnt bytes by bcnt. Each array transmission of the 2nd virial is separated from each other by an index, which is configured using SRCBIDX and DSTBIDX.

3rd Dimension or block (C): The 3rd dimension of a transport is made up of ccnt frames, each of which consists of bcnt arrays, and each array has acnt contiguous bytes. Each transmission of the 2nd virial is separated from the previous one with an index, the index is configured using SRCCIDX or DSTCIDX. Note that the reference point of the index depends on the type of synchronization, and once a trigger/sync event is received, the amount of data transmitted is controlled by the type of synchronization (Syncdim bit in opt), and in three dimensions only 2 synchronization types are supported: A-synchronous and ab-synchronous transmission.

Figure 3:acnt, bcnt, and ccnt definition

2.3.1 A synchronous mode

In a-synchronous transmission, each EDMA3 synchronization event causes a 1th-dimensional transmission of acnt bytes, or an array of acnt bytes. In other words, each event/TR packet passes only one array of transmission information. Thus, in order to serve a param set completely, bcnt x ccnt events are required.

The array is always separated by Srcbidx and Dstbidx, as shown in Figure 4, where the starting address of the array n equals the origin of the array N-1 and the bidx of the destination.

Frames are always separated by Srccidx and Dstcidx, and for a A-synchronous transmission, after the frame is exhausted, the address update is the starting address of the last array by adding the srccidx/dstcidx to this frame, as shown in Figure 4,srccidx/ Dstcidx is the difference between frame 0 Array 3 and Frame 1 array 0. Figure 4 shows a 3 (ccnt) frame, 4 (bcnt) array per frame, and a-synchronous transmission of N (acnt) bytes per array. In this example, 12 synchronization events (bcnt x ccnt) are required to complete the transmission of a param set.

Figure 4:a Synchronous Mode Transfer (ACNT = N, bcnt = 4, ccnt = 3)

2.3.1 AB Synchronous mode

In ab-synchronous transmissions, each EDMA3 synchronization event causes a transmission of 2 dimensions, or one frame. In other words, every event. The/TR package contains information about an entire frame (1 frames with bcnt arrays, acnt bytes per array). , so that, in order to serve a param set completely, a ccnt event is required.

The array is always separated by Srcbidx and Dstbidx, as shown in Figure 5, where frames are always separated by Srccidx and Dstcidx.

Note that for ab-synchronous transmission, after the frame tr is released, the address update is the start address of the first array by adding the srccidx/dstcidx to this frame. This is different from a-sync. In other words, in a-synchronous transmission and ab-synchronous transmission, the meaning of Srccidx/dstcidx is completely different, it is important to note.

Figure 5 shows 3 (CCNT) frames, 4 (bcnt) arrays per frame, ab-synchronous transmission per array of n (acnt) bytes. In this example, a 3 (CCNT) synchronization event is required to complete the transmission of a param set.

Figure 5:ab Synchronous Mode Transfer (ACNT = N, bcnt = 4, ccnt = 3)

2.4 PaRAM

EDMA3 Controller is a ram-based structure, DMA or QDMA Channel transmission context (source/destination address, count, index, etc.) is programmed with a parameter Ram table, this RAM in edma3cc, called Param,param table is segmented into multiple param sets, Each param set consists of 8 4-byte param set entries (that is, a total of 32 bytes per param set), which includes typical DMA transfer parameters such as source address, destination address, number of transports, index, options, and so on.

The Param structure supports flexible ping-pong, cyclic buffering, channel linking, and automatic loading (linking). The contents of param are as follows:

a:128 a set of parameters.

B: 64 channels directly mapped, and can be used as a link, or if not used as a DMA channel can be used as QDMA set.

C: The remaining 64 channels can be used as link or QDMA set.

Figure 6:param Parameter set corresponds to address

set of 2.4.1PaRAM parameters

Each param parameter set is a 8 32bit word structure, as described in Figure 7, each param set parameter is composed of 16bit and 32bit parameters.

Figure 7:param Parameter Set

Configuration of the parameters:

OPT: Channel option parameters

SRC: Data transfer Source Address

ACNT: The dimension of one-dimensional data

BCNT: Dimension of two-dimensional data

DST: Destination Address first address

DSTBICX: Destination address two-dimensional index

SRCBIDX: Source address two-dimensional index

Bcntrld and Link:link mode parameter settings

Dstcicx and Srccidx: three-dimensional address index for source and destination addresses

Cnnt: three dimensional dimension setting

2.4.2 opt parameter configuration

Opt main parameter configuration:

Itcchen: Once the TC completes the link to enable. The 3-D mode AB synchronization mode must be enabled to update the three-dimensional data address.

A synchronous mode 2 D 3 D data transfer must be enabled to update the first address.

Tcchen: The transfer completes the link enable, that is, the last TR to complete the production link.

Itcinten: A TC is completed to produce interrupt enable, that is, every time the TC is completed to produce an interrupt.

Tcinten: Interrupt is generated when the transfer is complete, that is, the last TC completed.

TCC: The transfer completion code, which tells the edmac3cc to transmit the completed code, is used for chain mode to link the next channel, and interrupt generation.

Tccmode: Transmission Completion code sending mode, including the normal mode and the pre-completion mode, the general mode is the normal transmission after the completion of the transfer of TCC, the pre-completion mode is the EDMA3CC after the submission of a TC is sent to the TCC that the transfer is completed, this mode, The TC may also be transmitting data when chain or interrupts are triggered.

The width setting of the Fwid:fifo is used to set the SAM or dam to fixed address mode.

The static setting of the Static:param parameter, 0 for non-static: When a TC transfer is completed param the parameter set is updated or connected, the AB mode three-dimensional mode is set to non-static, a-mode two and three-dimensional mode are set to non-static.

Syncdim: Settings for the synchronous mode of transmission, a synchronous mode or AB sync mode.

DAM: Destination address mode, address increment mode, and fixed address mode.

SAM: Source address mode, address increment mode, and fixed address mode.

2.5 EDMA3 Trigger mode:

EDAM3 has three kinds of triggering methods: Event trigger mode, manual trigger mode, chain contact hair mode

Event triggering methods typically serve peripherals, systems, or requests that generate external events.

The data transfer between the EDMA and the serial port can be triggered by the event.

Manual trigger mode: The corresponding transmission is triggered by the CPU to the ESR register corresponding to the position.

Chain Contact Hair Mode: is a transmission after the completion of the automatic triggering of other transmission mode.

The main difference between QDMA and dam is that the triggering method is different, the QDMA channel is automatically triggered when the trigger word is written, and the trigger word in the Param set can be programmed.

2.6 Linking transmission

The channel control of the EDMA provides a mode of connection transmission in which any one of the parameter sets in the parameter set can be overloaded with the other set of parameters in the Param map, and his main application is to apply the ping-pong buffer, and some cyclic transmissions, which do not require the transmission of CPU interrupts. The linking mode is set to set the static position bit 1 in opt, that is, the Param parameter to non-static mode.

A transfer must be connected to the other Param, and if this is the end of the transmission, the Param must be connected to NULL.

2.6 Chain Transmission

EDMA after the data handling of one channel is completed, it can link to other channels, continue to transmit data, do not need the CPU to send command, the response of time is the response of the chain event of three responses in the DMA event response.

Chain link mode and link connection mode is completely different mode, chain mode does not param set parameter update, but one channel transmission complete directly triggered another channel, achieve continuous data handling effect, However, the link mode is the constant update of the parameters on the same channel, thus achieving continuous data handling effect.

There are also two different ways to set up in chain mode: Transfer complection Chaining is the link to other channels after this data transfer is completed.

Intermediate transfer completion chaining is automatically linked to this channel at the end of this data transfer at the same time.

Two models correspond to Tcchen and Itcchen in opt

2.7 Transmission Queue

EDMA has three transmission queues: the queue of events is also part of the EDMA3 channel controller, EDMACC sends data handling events through the queue controller to the EDMATC start data handling. Each transmission queue is a depth of 16 events.

Q0 is associated with TC0, Q1 is associated with TC1, Q2 is associated with TC2, each queue is a FIFO queue, when an event arrives at the head of the queue, the queue controller transfers the event to a EDMATC to control the transmission.

8 Dmaqnumn can be used to control the 64 DMA channels into different queues, the default Q0 event priority is the highest, Q1 second, Q2 the lowest priority, but three queue priority can be set by the Quepri to change.

2.8 Interrupts

EDMA transmit data can produce two different interrupts: final transfer completion and intermediate transfer completion

Both interrupt modes are controlled by Tcinten and Itcinten in OPT, and if Tcinten=1 itcinten=0, interrupts are generated at the end of the last TC transfer, if tcinten=0 Itcinten = 1 interrupts are generated once each TC is completed.

For example acnt = 3, bcnt = 4, ccnt = 5.

Data Handling register configuration between 3:DDR and SRAM

3.1 One dimensional data handling

Table 3.1.1:opt Configuration

Reserved	Privid	Tcchen	Tcchen	Itcinten	Tcinten	Reserved	TCC
R	R	0	0	0	1	R	0
TCC	Tccmod	Fwid	Reserved	STATIC	Syncdim	DAM	SAM
31	0		R	1	0	0	0

Table 3.1.2:param Parameter Set configuration

Opt	Channel Options Parameter (OPT)
Data Handling Source Address	Channel Source Address (SRC)
1	128	Count for 2nd Dimension (BCNT)	Count for 1st Dimension (ACNT)
Data Handling Destination Address	Channel Destination Address (DST)
0	0	Destination bcnt Index (DSTBIDX)	Source bcnt Index (SRCBIDX)
0	0xFFFF	Bcnt Reload (Bcntrld)	Link Address (link)
0	0	Destination ccnt Index (DSTCIDX)	Source ccnt Index (SRCCIDX)
R	1	Reserved	Count for 3rd Dimension (ccnt)

3.2 Two-dimensional data handling

A Synchronous Mode:

Table 3.2.1:opt Configuration

Reserved	Privid	Tcchen	Tcchen	Itcinten	Tcinten	Reserved	TCC
R	R	1	0	0	1	R	0
TCC	Tccmod	Fwid	Reserved	STATIC	Syncdim	DAM	SAM
31	0	0	R	0	1	0	0

AB Sync mode:

Table 3.2.2:opt Configuration

Reserved	Privid	Tcchen	Tcchen	Itcinten	Tcinten	Reserved	TCC
R	R	0	0	0	1	R	0
TCC	Tccmod	Fwid	Reserved	STATIC	Syncdim	DAM	SAM
31	0	0	R	1	0	0	0

Table 3.2.3:param Parameter Set configuration

Opt	Channel Options Parameter (OPT)
Data Handling Source Address	Channel Source Address (SRC)
16	128	Count for 2nd Dimension (BCNT)	Count for 1st Dimension (ACNT)
Data Handling Destination Address	Channel Destination Address (DST)
128	128	Destination bcnt Index (DSTBIDX)	Source bcnt Index (SRCBIDX)
0	0xFFFF	Bcnt Reload (Bcntrld)	Link Address (link)
0	0	Destination ccnt Index (DSTCIDX)	Source ccnt Index (SRCCIDX)
R	1	Reserved	Count for 3rd Dimension (ccnt)

3.3 Three-dimensional data handling

Table 3.3.1:opt Configuration

Reserved	Privid	Tcchen	Tcchen	Itcinten	Tcinten	Reserved	TCC
R	R	1	0	0	1	R	0
TCC	Tccmod	Fwid	Reserved	STATIC	Syncdim	DAM	SAM
31	0	0	R	0	1	0	0

Table 3.3.2:param Parameter Set configuration

Opt	Channel Options Parameter (OPT)
Data Handling Source Address	Channel Source Address (SRC)
16	32	Count for 2nd Dimension (BCNT)	Count for 1st Dimension (ACNT)
Data Handling Destination Address	Channel Destination Address (DST)
32	32	Destination bcnt Index (DSTBIDX)	Source bcnt Index (SRCBIDX)
0	0xFFFF	Bcnt Reload (Bcntrld)	Link Address (link)
16 * 32	16 * 32	Destination ccnt Index (DSTCIDX)	Source ccnt Index (SRCCIDX)
R	8	Reserved	Count for 3rd Dimension (ccnt)

3.4 Data handling efficiency test

Testing of data handling efficiency:

A:EDMA3 a synchronous mode and AB synchronous mode for efficiency handling testing

Using the cycle function to test the handling of a 128*128 byte of data, consumes 9,116 cycles in AB mode, a mode requires 25830,ab synchronization mode is much faster than a synchronous mode, nearly 3 times times the time.

B:EDMA testing of the efficiency of the handling of data between DDR: (Sample code Edma_effciency_test ();)

The object of the sample code handling is a piece of data 16*1024, which, in AB synchronous mode, copies the data directly with the memcpy (), consuming 16,371 cycle.

When using DMA for data handling, it takes 30,897 cycles of time.

When using DMA to place this 16K data in a different 16-block area, the time required is 33,944 cycles.

It can be seen that the addressing of DDR between addresses that are not neighbors is much slower than addressing between adjacent addresses.

Because the EDMA is running in the DSP frequency of 1/3, that is, at 197MHZ frequency, so EDMA in the data handling is slower than the CPU directly to copy the data, but, EDMA in the data handling is not required CPU interference, in fact, does not consume cycle, So, EDMA still greatly improve the efficiency of the CPU.

3.5 between DDR and SRAM data handling cache consistency issues

The data handling register setting between DDR, the register setting of the DDR and SRAM handling, and the register setting of the SRAM handling are the same. You only need to change the source and destination address.

However, once the destination address is DDR, it is set to the DDR and SRAM consistency issues.

Cache is invalid: Because the EDMA is not interfering with the CPU data handling, but the CPU reads the data through the cache to read the data, when the EDMA destination address is set to DDR, the CPU does not know that the DDR data has changed, Of course, it will not update the contents of the cache, so when the CPU reads the contents of the block DDR is still not updated in the cache data, this situation needs to be the original DDR data corresponding to the cache set invalid, new write to the cache value, You can guarantee the consistency of the DDR and the cache. The corresponding Cache invalid function is: Cache_invalid ();

Cache writeback: The same DMA in the handling of data, there may be another situation, the processor when processing data will be stored in the cache, the data in the cache may not yet come to the urgent write to memory, when the DMA to the peripheral to write data supplied by the processor, DMA will get data directly from the DDR, moving to the peripheral, and this data is not intended to carry the data, in this case to call the cache writeback function, before the DMA data transfer to write the cache data into the DDR, to ensure the consistency of the DDR and cache data.

4:EDMA control of data handling between DDR and serial port

Due to the EDMA of 64 events and peripherals there is a fixed channel correspondence. The test program is sent using 25 channels and receives 24 channels.

Figure 9: The event triggers a fixed UART event corresponding to a fixed channel.

First write out the relevant parameter settings of the EDMA channel settings, the UART can only use a synchronous mode for data handling. The following is the settings for the OPT parameter: (both receive and send can be set according to this setting)

Table 4.1:uart sending data in DDR OPT configuration

Reserved	Privid	Tcchen	Tcchen	Itcinten	Tcinten	Reserved	TCC
R	R	0	0	0	1	R	0
TCC	Tccmod	Fwid	Reserved	STATIC	Syncdim	DAM	SAM
25	0	0	R	0	0	0	0

Table 4.2:uart sending data param parameter set configuration in DDR

Opt	Channel Options Parameter (OPT)
DDR Send Source Address	Channel Source Address (SRC)
1	1024	Count for 2nd Dimension (BCNT)	Count for 1st Dimension (ACNT)
THR register with Send mode set to UART	Channel Destination Address (DST)
0	1	Destination bcnt Index (DSTBIDX)	Source bcnt Index (SRCBIDX)
0	0xFFFF	Bcnt Reload (Bcntrld)	Link Address (link)
0	0	Destination ccnt Index (DSTCIDX)	Source ccnt Index (SRCCIDX)
R	2	Reserved	Count for 3rd Dimension (ccnt)

Table 4.3:uar receive data in DDR opt configuration

Reserved	Privid	Tcchen	Tcchen	Itcinten	Tcinten	Reserved	TCC
R	R	0	0	0	1	R	0
TCC	Tccmod	Fwid	Reserved	STATIC	Syncdim	DAM	SAM
24	0	14	R	0	0	0	0

Table 4.4:uar receive data in DDR param parameter set configuration

Opt	Channel Options Parameter (OPT)
THR register with receive mode set to UART	Channel Source Address (SRC)
1	1024	Count for 2nd Dimension (BCNT)	Count for 1st Dimension (ACNT)
DDR Storage Address	Channel Destination Address (DST)
1	0	Desti