TI DSP tms320c66x SPI Nor Flash multi-core program Burn Write

Reproduced in the original: http://blog.csdn.net/hw5226349/article/details/50767454 thank you very much.

After a period of research finally the tms320c6657 single-core and dual-core SPI Nor Flash program to write tune. Tools are predecessors of the work, there is a need to leave the mailbox, I have free to send.

Principle reference Chanfong's "TI c66x series DSP multi-core boot research" paper.

All processes of the loader through nor flash burning: (in No-boot mode)

First, talk about the tool chain:

hex6x with the. rmd file (several. rmd files are required for a few.) files, which describe output control, boot options, memory options, and so on) to generate the boot table required by the on-chip bootloader loader, the output file is *.btbl

mergebtbl Link *.btbl in a certain order

b2i2c convert *.btbl to I2C/SPI format, divide boot table into 0x80 byte block and append length and checksum (checksum)

The B2ccs converts the *.btbl.i2c into a. dat format received by the. I2C.CCS,CCSV5 IDE and loads it into the DDR3. and manually change 9th line 51 in I2crom.ccs to 00.

romparse Merge boot table and boot parameter table, parameter configuration table file *.map as input.

Byteswapccs Convert. Dat to a big-endian mode that ROM bootloader code can recognize

Second, the tool chain is written as a batch file

1. Single-core. dat file generation

hex6x SIMPLE.RMD

B2I2C Simple.btbl SIMPLE.BTBL.I2C

B2ccs SIMPLE.BTBL.I2C Simple.i2c.ccs

Romparse Nysh.spi.map

Pause//Pause, change 9th line 51 in I2crom.ccs to 00

Byteswapccs I2crom.ccs Spirom_le.dat

2. Dual-core. dat file generation

hex6x CORE0.RMD

hex6x CORE1.RMD

Mergebtbl Core0.btblcore1.btbl Multi_core.btbl

B2I2C Multi_core.btbl SIMPLE.BTBL.I2C

B2ccs SIMPLE.BTBL.I2C Simple.i2c.ccs

Romparse Nysh.spi.map

Pause//Pause, change 9th line 51 in I2crom.ccs to 00

Byteswapccs I2crom.ccs Spirom_le.dat

Blue is different from the single-core. dat file generation, the other is the same.

Third, *.dat burning writing process

1.2 LED test Engineering, successfully compiled and generated 2. Out files, generate an. out file must be named Core0.out, Core1.out

2. Copy the 2. Out files to the Spi_bootloader tool chain path, double-click the Spibootmulticore.bat batch file, start generating the file, get the Spirom_le.dat

3. Adjust the EVM board to No-boot mode, and the dial switch corresponds to SW3~SW5 1000 0000 0000 0000 (0 corresponds to on 1 off)

4. Open the MCSDK nor-writer project, open the Nor_writer_input.txt under the Project Bin folder, modify the input file name Spirom_le.dat and copy Spirom_le.dat to mcsdk_xxxx\ Under Tools\writer\nor\evmc667xl\bin Path

5. Link project, such as PC pointer stop at main function entrance, open view--memory Browser, input 0x80000000,load memory select Spirom_le.dat, (Automatic) hook on use the header ... Re-confirm that start address is 0x80000000,length for the length of spirom_le.dat (in Word) to begin pouring into the DDR.

6. Write the project run, note that the console output shows the same size as the length of the file burned into flash, the burn is successful, at this time the unit is bytes.

7. Last DIP switch dial to ROM SPI boot mode, sw3~sw5 1011 0000 0010 0000, power off restart

Fourth. Multi-core boot process

The c66x DSP has a cured rom inside, which holds the boot code (ROM bootloader). Whenever the DSP starts, the code is automatically read from here and executed. The code executed here is immutable, and its role is to initialize the kernel (such as the PLL, etc.) according to the pin configuration of the DSP, and to complete the boot processing of different modes. All cores execute the same piece of code. Different cores are differentiated by dnum (nuclear numbered index) at execution time. The initial operation is done by CORE0. So while CORE0 initializes other peripherals, the other core performs the associated code mapping IPC interrupts, configures the appropriate registers, and then enters the idle state, waiting for the CORE0 IPC interrupt to initiate. In short, other cores execute the first line of code under the CORE0 command.

The Boot Magic address is a fixed piece of memory for each core. This word holds the C program entry address _c_int00 () that needs to be redirected after each core initialization. The boot magic address for tms320c6657/tms320c6670 is 0X1X8FFFFC because they L2 ram size 1MB. The boot magic address for tms320c6678 is 0X1X87FFFC, because L2 RAM is only 512KB.

If the multi-core DSP is compiled separately by the same set of projects, then each kernel memory allocation is identical. Core0 after reading the Boot Magic Address (0X108FFFFC) of its own kernel, the Boot Magic address (* for the nuclear number) of the other cores can be obtained after adding 0x0*000000. However, if each kernel compiles its own independent project, the memory mapping relationship of each variable is no longer the same, then the value from the boot Magic address of the CORE0 will not be able to calculate the other kernel corresponding address. At this point, you can only record the magic address of each kernel in advance, and then write to the user initialization code of kernel 0.

Upon completion of all of the above operations, the CORE0 needs to write interrupts to the IPCGRX register of each core to wake up the other cores ' normal operating state. The 31-4 bit of the IPCGRX register is the IPC interrupt source index, which can support up to 28 interrupt sources, the sample can be set to full 0, bit 3-1 is reserved bit and can be arbitrarily assigned. Therefore, the IPC interrupt can be triggered as long as the minimum bit is assigned to 1.