Timequest Timing Analyzer for Timing Analysis (ii)

Iv. timing Analysis of the DAC7512 controller with Timequest

When timing constraints on an object, the first thing to be able to correctly identify it, timequest in the design of the components according to the attributes of the classification, we are under the time constraint, we can use the command to find the corresponding category of an object.

Timequest to the design of the components of the classification of the main cells,pins,nets and ports several. Registers, gate circuits and the like cells, the design of the input and output port is ports, the input and output pin of register, gate circuit and so on is the connection between pins;ports and pins is nets. Refer to (this figure is from Altera time Quest's instructions for use).

The following is a sequence analysis of the DAC7512 controller according to the process described in the third part of this article, using Timequest as the basic operating procedure for timing analysis. the part of building and precompiling a project is relatively simple and involves just a few basic operations of quartusii, where we do not have a specific narrative. It mainly describes how to add timing constraints to your project and how to perform timing validation. First create an SDC file with the name consistent with the top layer of the project, and then add the timing constraint by following the steps below.

1. Create a clock

the first step in adding a timing constraint is to create a clock. To ensure the accuracy of the STA results, all clocks in the design must be defined and all relevant parameters of the clock specified. The timequest supports the following clock types:

A) reference clock (base clocks)

b) virtual clock (Vsan clocks)

c) Multi-frequency clock (multifrequency clocks)

d) generate clock (Generated clocks)

When we add a timing constraint, the first reason for creating the clock is to refer to the associated clock for the rest of the timing constraints.

Reference clock:

The reference clock is the original input clock that is entered into the FPGA. Unlike the clock output by the PLLs, the reference clock is typically generated by an off-chip crystal oscillator. The reason for defining the base clock is that other generation clocks and timing constraints are usually referenced by the reference clock. Obviously, in the DAC7512 controller, the clk_in is the reference clock. We use the following command to create this reference clock:

1 create_clock-name clk_in-period -waveform {0 } [get_ports {clk_in}]

Where Create_clock is the command to create the clock, followed by various options for the command. Where the-name clk_in option gives the name of the clock, which is clk_in. -period 40 gives the cycle of the clock, which is 40ns. -waveform {0 20} gives the duty ratio of the clock, which is 50/50. The last [get_ports {clk_in}] is a nested TCL command, giving the clk_in corresponding port, which is actually the input pin of the clk_in.

After adding the above command in the SDC file, compile the design in quartusii and then open timequest with the tools–> timequest time Aanlyzer command. In the Timequest Tasks window, locate the report clocks and double-click on it, Timequest will give the clock information that was successfully added in the design on the right main window. As shown, you can see clk_in, whose type is the reference clock, the period is 40ns, the frequency of 25mhz,targets is clk_in, which means that the clock is connected to the clk_in port. This means that the command above Create_clock has correctly created the clock clk_in in the design.

In fact, for the Create_clock command, we can find its syntax through Quartus II's Help system (http://quartushelp.altera.com/current/). In Quartusii's help, you can find:

Syntax

Create_clock [-H |-help] [-long_help] [-add] [-name <clock_name>]-period <value> [-waveform <edge_list>] [< Targets>]

In addition, the Help system has a very detailed description of the command, and gives examples of various uses. Not just this one command, all commands can be found in the Help system. If you see a strange command, or if you don't know how to use it, the best way is to find it in the Help system.

PLL Clock:

above we created the reference clock. Below we create the clock for the PLL output. In Altera's FPGA, the PLL circuitry is added to the design through the ALTPLL IP library. is a typical ALTPLL structure diagram.

As you can see from the diagram, the parameters for the output C0 and C1 of the PLL are determined after we have selected the parameters of the reference clock and the PLL. So in the QUARTUSII environment, a simple command allows the software to automatically generate clock timing constraints for the PLL output.

Derive_pll_clocks

This command automatically creates the relevant timing constraints for the C0 and C1 of the PLL output. Similarly, add the command to the SDC file, compile it, and view the clock information in the timequest. As shown, Derive_pll_clocks added two clocks to the system, pll1|altpll_component|auto_generated|pll1|clk[0] and Pll1|altpll_component|auto_ GENERATED|PLL1|CLK[1]. As you can see, the clock is named after the "PLL hierarchy + clock port name" rule. The clock type is created clock and the cycle frequency is set in the PLL. Duty_cycle is 50/50. Clock source is pll1|altpll_component|auto_generated|pll1|inclk[0], which is actually the clk_in we defined earlier. Derive_pll_clocks automatically searches the time domain network and creates the PLL's output clock. You can also use the Create_generated_clock command.

Derive_pll_clocks's command format is: derive_pll_clocks [-create_base_clocks] [-use_tan_name]

option [[-create_base_clocks] automatically generates the input clock for the PLL, [-use_tan_name], by default, the name of the clock is the name of the output clock.

The Derive_pll_clocks command invokes the Create_generated_clock command to generate a derived clock on the output clock of the PLL, the source of the create_generated_clock is the input clock pin of the PLL, in the call Derive_ Before or after the Pll_clocks command, we must manually generate a base clock for the PLL as its input clock, and if we do not define this input clock, then the output clock of the PLL will not be available in the report, and the analyzer will give a warning:

The master clock for this clock assignment could no is derived.

Clock:<name of PLL output clock pin name> is not created.

So use the <-created_base_clocks> option to automatically generate input clock constraints for the PLL.

You can place the Drive_pll_clocks command in your SDC so that the Derive_pll_clocks command automatically detects any changes to the PLL, and when the Derive_pll_clocks command is used, the PLL is automatically constrained.

It is convenient to create PLL-related clocks with the derive_pll_clocks command, but the downside is that the name of the clock is too complex, and when we add the timing constraints associated with this clock, we have to use this long-named clock, which is error-prone and less readable. Therefore, it is recommended to use the Create_generated_clock command to create the PLL Clock Create_generated_clock command syntax as follows, you can find a detailed explanation of each parameter from the QUARTUSII Help system.

Syntax

Create_generated_clock [-H |-help] [-long_help] [-add] [-divide_by <factor>] [-duty_cycle <percent>] [-edge_shift <shift_list>] [-edges <edge_list>] [-invert] [-master_clock <clock>] [-multiply_by <factor>] [-name <clock_name>] [-offset <time>] [-phase <degrees>]-source <clock_source> [<targets>]

You can use the following command to create the two clocks of the PLL C0 and C1. We name the clocks clk25m and Clk50m,source clock for clk_in.

Create_generated_clock-name Clk25m-source clk_in-duty_cycle 50.000-multiply_by 1-master_clock {CLK_IN} [get_pins {PLL 1|altpll_component|auto_generated|pll1|clk[0]}]

Create_generated_clock-name Clk50m-source clk_in-duty_cycle 50.000-multiply_by 2-master_clock {CLK_IN} [get_pins {PLL 1|ALTPLL_COMPONENT|AUTO_GENERATED|PLL1|CLK[1]}]

The clocks created with these two commands are the same as the clocks created by the derive_pll_clocks command, just defining a different name for the clock. Of course we can also use the Create_generated_clock command in Derive_pll_clocks to name the clock. Similarly, the result of creating a clock can be viewed in timequest as shown in the above method.

Note that, derive_pll_clocks, if [-create_base_clocks] is not selected, this command does not ports create base clocks for the input clock that drives the PLL, if this option is selected, The reference clock is automatically created for the input port of the PLL.

So far, we have created the reference clock for the PLL and the two clocks clk25m and clk50m for the PLL output.

DA_SCLK Clock:

in the Tasks window of timequest, select the report unconstrained Paths command, and timequest reports all situations that require constraint but are not actually constrained. In the report, under the Unconstrained path list, we can view the reports. Double-click the clock status Summary to see all the clocks in the main window. See, it is clear that the software identifies the DA_SCLK as the clock signal under the DAC7512 module, but we do not add a constraint to the clock, so the clock is displayed in red. Next we're going to create this clock.

DA_SCLK is obtained by means of a two-way circuit using clk50m. So its source clock is clk50m. However, when we use the Create_generated_clock command to create the clock, in the-source parameter, but not directly using clk50m, but must use the clk50m corresponding PIN, that is pll1|altpll_component| AUTO_GENERATED|PLL1|CLK[1]. This is mainly because the-source parameter only supports pins,ports and registers. the DA_SCLK is generated by the clk50m via a two-way circuit with the following code:

1 RegDA_SCLK;2 3  always@(Posedgeclk50mor NegedgeRESET)4 5 begin6 7 if(~RESET)8 9DA_SCLK <=1'B0;Ten  One Else A  -DA_SCLK <= ~DA_SCLK; -  the End

View Code

as you can see, essentially DA_SCLK is the output of a register, so use the get_registers command to get the DA_SCLK. The DA_SCLK is generated by the clk50m via a two-way circuit, so the-divide_by parameter should be 2. to summarize, create DA_SCLK with the following command:

Create_generated_clock-name da_sclk-divide_by 2-source [get_pins {pll1|altpll_component|auto_generated|pll1|clk[1] }] [Get_registers {DAC7512:DAC7512|DA_SCLK}]

So far, all 4 clocks in the DAC7512 controller have been created. As shown in the following:

when we look at the clock Status Summary in unconstrained paths in timequest, we will find that all the clocks have been added to the constraint.

   

Timequest Timing Analyzer for Timing Analysis (ii)