Timequest Timing Analyzer for timing Analysis (iv)

Set input/output delay (input/output delay). First look at the input delay.

The system shown below is something we often encounter when designing digital circuits. External devices may be other integrated circuit chips, or other FPGAs, to be called External device in order to be separate from the FPGA we are discussing. The output of the register D1 in the External device is given to the register D2 in the FPGA. D1 and D2 belong to the same clock domain (CLK). To simplify the discussion, we assume that the delay between the CLK source and the two registers is equal, i.e. the delay CLK1 equals the delay CLK2. At this time, D1 's CLK end to D2 's D-end forms a complete timing path.

However, when we do time series analysis of FPGA, the software only knows the timing information inside the FPGA, it is not clear to external device. So we have to add additional constraints to reflect the timing information outside of the FPGA. In general, we use input delay to represent the delay of the input signal relative to CLK. That is, we use the red line to represent the part. For the sake of discussion, we refer to the part of the FPGA's inner Blue Line as chip delay. If we can give the size of input delay, then the software can calculate the size of the chip delay, thus ensuring that the timing path conforms to the design requirements.

In general, External device spec gives the size of input delay. When we do FPGA timing analysis, we only need to use the command to add input delay to the constraint.

The following is the syntax for input delay, which is described in detail in the Help system of Quartus II.

Syntax

Set_input_delay [-H |-help] [-long_help] [-add_delay]-clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [- Rise] [-source_latency_included] <delay> <targets>

Since there is no need to set the input delay signal in the DAC7512 controller, here are a few examples of the general input delay, which are not related to the design of the DAC7512 controller.

In the above discussion, we assume that the latency of CLK to D1 and D2 is equal, but in some cases the latency of CLK may be different, so when you define input delay, you need to consider the difference between the CLK delay. The specific calculation method please consider, you can also refer to the relevant parts of the Timequest document, here is no longer a narrative.

then look at the output delay.

is an example of an output Dleay, similar to the input delay mentioned above. This is often the case when designing digital circuits. Similarly, External devices may be other integrated circuit chips, or other FPGAs, to be separated from the FPGA we are discussing, called External device. The output of the register D1 of the FPGA in the figure is given to the register D2 of the external device. D1 and D2 belong to the same clock domain (CLK). To simplify the discussion, we assume that the delay between the CLK source and the two registers is equal, i.e. the delay CLK1 equals the delay CLK2. At this time, D1 's CLK end to D2 's D-end forms a complete timing path.

Similarly, when timing analysis of the FPGA, the software only knows the timing information inside the FPGA, it is not clear to the external device situation. So we have to add additional constraints to reflect the timing information outside of the FPGA. In general, we use output delay to represent the delay of the output signal from the FPGA's external route relative to CLK. That is, we use the Blue Line to represent the part. For the sake of discussion, we refer to the part of the inner red thread of the FPGA as chip delay. If we can give the output delay size, then the software can calculate the chip delay, thus ensuring that the timing path conforms to the design requirements.

In general, External device spec gives the required output delay size. When we do FPGA timing analysis, we only need to use the command to add output delay to the constraint.

The following is the syntax for output delay, which is described in detail in the Help system of Quartus II.

Syntax

Set_output_delay [-H |-help] [-long_help] [-add_delay]-clock <name> [-clock_fall] [-fall] [-max] [-min] [-reference_pin <name>] [- Rise] [-source_latency_included] <delay> <targets>

Also gives two general examples:

Set_output_delay-clock CLK 0.5 [all_outputs]set_output_delay-clock clk-clock_fall 0.5 [get_ports myout*]

Now we discuss the output delay of the DAC7512 controller outputs, taking the da_din signal as an example. The Da_din and DA_SCLK of the DAC7512 controller and the DAC7512 din and SCLK are connected in the following manner.

You can see that the clocks of D1 and D2 are clk50m. The delay of clk50m to D1 and D2 is Delay1 and Delay6 respectively. Depending on the characteristics of the FPGA, Delay1 and Delay6 can be considered equal. Delay4 and Delay5 are two signal lines on the PCB delay, you can think that the two are equal. The FPGA design satisfies the delay (Delay2) of the D1 to DA_SCLK port and the delay of D2 to Da_din Port (DELAY3) to meet the requirements for DIN input delay on DAC7512 datasheet (for FPGAs, is the output delay of Da_din).

The datasheet of the DAC7512 gives the timing requirements of DIN and SCLK on the DAC7512 pins. As shown in the following two images. You can see that with PORT_DA_SCLK as the benchmark, the maximum output delay for Da_din is (20-4.5) and the minimum value is 5.

For us, Delay2 is a relatively hard-to-determine value, but we can actually use the PORT_DA_SCLK clock that defines DA_SCLK as the source of the software to give us the value of Delay2. Create a PORT_DA_SCLK clock with the following command.

Create_generated_clock-name port_da_sclk-divide_by 1-source [GET_REGISTERS{DAC7512:DAC7512|DA_SCLK}] [Get_ports DA_ SCLK]

This allows us to define the output delay of the Da_din with the Set_output_delay command.

Set_output_delay-clock Port_da_sclk-clock_fall-max 14.5 [get_ports da_din]set_output_delay-clock Port_da_sclk-clock _fall-min 5 [Get_ports Da_din]

Timequest Timing Analyzer for timing Analysis (iv)