Timequest Timing Analyzer for Timing Analysis (v)

3. Creating Timing Exceptions

Once the clock is created and the input/output delay is defined, the design can be time-series analyzed according to these constraints. By default, the software analyzes all timing paths that need to be checked according to the 1T principle. In combination, layout and routing, the tool will also be based on timing constraints, as much as possible to make all timing path to meet the requirements of 1T. But the tool is not omnipotent, if the design requirements are too high, some timing path may not meet the design requirements, so do not meet the design requirements of the timing path will be given in the form of timing violation.

In many cases, the structure and functionality of the design does not require that all timing paths meet 1T requirements, and even some timing paths do not have timing requirements at all, such as asynchronous reset signals. At this time, it is possible to set a relatively loose timing constraint for this class of timing path or not to make timing requirements, called timing exceptions.

There are two common ways to set timing exception: false path and multicycle path. First to discuss false path.

False path is the timing path that does not require attention to its timing. If a timing path is set to False path, the software will automatically ignore the timing path when doing time-series analysis and do not analyze it. Before the clock group, it was said that if the two clocks were set to different groups, the software would not analyze the timing path of the two clock times. How is the software implemented? In fact, when setting two clocks for different groups, the software implied action is to set all the timing path between the two clocks to false path, so as to achieve the purpose of not analyzing them.

You can use the Set_false_path command to set a timing path to false path. Here is the syntax for Set_false_path:

Syntax

Set_false_path [-H |-help] [-long_help] [-fall_from <names>] [-fall_to <names>] [-from <names>] [-hold] [-rise_from <names>] [-rise_to <names>] [-setup] [-through <names>] [-to <names>]

In this command,-from is used to define the starting point of the timing path,-through is used to define the points that timing path passes,-to is used to define the end point of the timing path, and-hold and –setup can be used to define the scope of the command. is Setup/hold check, and the default is setup and hold are applicable. Additional parameters and more detailed descriptions can be referred to Quartusii's help system or SDC-related information.

in the design of DAC7512 Controller, because the working frequency is slow, the design is relatively simple, so there is no timing violation in the design, it is inconvenient to control the use of Set_false_path command in the real environment. In this way, the timing violation is produced by increasing the clock frequency. The clock clk25m and clk50m of the DAC7512 controller are adjusted to 75MHz and 150MHz respectively, and other related clocks change. The timing analysis results of the DAC7512 controller after changing the clock are reported with Timequest. The following is the result of the Setup check:

The results from summary of paths can be seen in the system existence of two timing path exists timing violation. Take timing violation The first timing path of the larger value is analyzed, the following is the details of the timing path:

The starting point of the timing path is dac7512:dac7512| DACSM[2], the end point is da_din,launch clock and latch clock respectively are DA_SCLK and PORT_DA_SCLK (falling edge), the slack value is-12.262. When you previously defined a constraint on a clock, the two clocks were defined as the same group. There is also more detailed information about this timing path, such as every point that timing path passes, and the delay between each cell or net, and so on, which is not described in detail here.

Set_false_path-from [Get_pins {dac7512| DACSM[2]|CLK}]-to [get_ports {Da_din}]

After adding this constraint, we look at the results of the timing analysis, and the setup situation is as follows:

The software now reports that only one timing path has timing violation, and that the timing path with the above set to False path is missing. But it doesn't really mean that the timing of the timing path above is not a problem, the original problem still exists, even worse, but we set it to false path, the software will not analyze it. This requires that the use of Set_false_path must be cautious. You can use this command only if you do not have to pay attention to the timing of a timing path, otherwise the software will not do any analysis of it, the probability of the problem will be larger. when using set_false_path commands, it is also important to note that the starting point of timing path is actually the clock end of the register dacsm[2], using [get_pins {dac7512| DACSM[2]|CLK}] to get.

Discuss multicycle path again.

in general, the signal is changed at the beginning of the timing path (that is, the first clock edge), and terminate collects the signal at the end of the timing path (i.e. the second clock edge). In this case, a timing check would need to be done by 1T, which is one of the most common scenarios in design. But if the signal changes along the first clock, and the terminate side collects the signal along the third clock, then there is no need to ensure that the signal is passed to the end point along the second clock, that is, it does not need to do a 1T check, but a 2T check, that is, to ensure that the signal arrives at the end of the third clock edge. By analogy, the timing path can be checked for NT (n > 1), at which point the timing path is referred to as multicycle path.

setting a timing path to multicycle path, regardless of the actual number of multi, actually reduces the timing requirements for the timing path of the strip.

You can use the Set_multicycle_path command to set a timing path to multicycle path. The following is the syntax for the Set_multicycle_path command:

syntax

Set_multicycle_path [-H |-help] [-long_help] [-end] [-fall_from <names> ] [-fall_to <names> ] [-from <names> ] [-hold] [-rise_from <names> ] [-rise_to <names> ] [-setup] [-start] [-through <names> ] [-to <names> ] <value>

Like Set_false_path, in the command,-from defines the starting point of the timing path,-through defines the point through which the timing path is defined,-to is used to define the end of the timing path, in addition to-hold and – Setup defines the scope that this command applies to when Setup/hold check is used, and the default is that Setup and hold apply. Another important parameter is value, which is used to define the value of the multi directly, if value=2 is set, then multicycle 2 path, if value=3, is multicycle 3path. Additional parameters and more detailed descriptions can be referred to Quartusii's help system or SDC-related information.

assuming that the timing path mentioned above is multicycle 2 path, you can use the following command to make a timing constraint on the timing path:

Set_multicycle_path-setup 2-from [Get_pins {dac7512| DACSM[2]|CLK}]-to [get_ports {da_din}]set_multicycle_path-hold 1-from [get_pins {dac7512| DACSM[2]|CLK}]-to [get_ports {Da_din}]

Note that if the timing path is multicycle 2 path during the Setup check, the timing path is multicycle 1 path when the hold check is made, and so on.

It is also very important to note that if the resouce has more than one terminate, the resource is the starting point of the timing path when the multicycle path is set, and its multiple terminate and the starting point should be handled by the CDC circuit, for more information about this , you can refer to the relevant CDC information.

Set_false_path and Set_multicycle_path These two commands, have different application occasions and backgrounds. But the same thing is, it is triggered from the actual structure of the system to reduce the timing requirements of the whole system. When using these two commands, it is important to make sure that the design itself is in line with the requirements, otherwise it is easy to issue timing problems.

There are also two other commands, namely Set_max_delay and Set_min_delay. Not recommended for everyone, so there is no more introduction here, interested friends can go to find information about SDC.

Timequest Timing Analyzer for Timing Analysis (v)