TMS320C55X's command system __c

c55x accesses data space, memory map registers, register bits, and I/O space through the following three addressing methods:Absolute addressing by specifying a constant address in an instruction to complete addressing direct addressing using address offset addressing indirect addressing using pointers to complete addressing 1. Absolute addressing mode

C55x has an absolute addressing mode:

1.1 K16 Absolute Addressing
The operand is *abs16 (#k16), and the unsigned constant of the k16:16 bit
7-bit registers DPH and K16 cascaded into a 23-bit address for access to the data space

1.2 K23 Absolute Addressing
Operand is * (#k23), "Unsigned constant of k23:23 bit"
1.3 I/O absolute addressing
Operand is *port (#k16), "k16:16 bit unsigned constant"
Use a mnemonic directive with the operand of Port (#k16) (no * before operand *) 2. Direct addressing mode

Note: DP and SP repel each other, through the St1_55 cpl position to choose. 0 dp,1 SP,

2.1 DP Direct addressing

High 7-bit is provided by DPH, used to determine master data page

The low 16-bit is made up of two parts:

Dp

7-bit offset (doffset)

2.2 SP Direct addressing

SPH determine high 7-bit address

16-bit addresses are determined by SP and 7-bit offsets, with an offset range of 0~127

The extended data stack pointer is formed by the SPH and SP XSP

2.3 Register bit addressing operand is @bitoffset only register bit test, position, clear 0, take back instruction to support this addressing mode

2.4 PDP Direct addressing

Port () qualification, which specifies the I/O space to be accessed. Rather than a data storage unit. 3. Indirect addressing mode

3.1 AR indirection accesses the data space st2-55 by a secondary register ARN (n=0,1,2,3,4,5,6,7) ARMS bit determines the operation type of AR indirection ARMS=0,DSP mode: CPU provides efficient executive function of DSP enhanced applications ARM S=1, control mode: The CPU can optimize the length of the code

3.2 Dual-AR indirection accesses two data storage units at the same time through 8 secondary registers (AR0~AR7): Executes a command that completes two 16-bit data space access and executes two instructions in parallel

3.3 CDP indirection use factor data pointers (CDP) to access data space, register bits, and I/O space

The 3.4 coefficient indirection supports the following arithmetic instructions: Fir filter multiplication multiplier minus double multiplication or double multiplication minus instruction system

1 Concurrent execution

characteristics of instruction parallelismBuilt-in parallelism in a single instruction-implicitly parallel modeFor example:Mpy *ar0, *CDP, AC0::Mpy *ar1, *CDP, AC1 the parallelism between user-defined two instructionsFor example:Mpym *ar1–, *CDP, AC1||XOR AR2, T1 built in parallel with user-defined blending     For example:Mpym t3=*ar3+, AC1, AC2 | | MOV #5, AR1rules for instruction parallelismThe total length of two instructions cannot exceed 6 bytes in the execution of the instruction, there is no resource conflict between the operator, the address generation unit, and the bus. One of the instructions must have and exercise the ability bit or two instructions to conform to the soft-double parallel conditionssituations in which parallelism cannot be usedUse the immediate number addressing methodFor example:*ABS16 (#k16); * (#k23); port (#k16); *arn (K16); *+arn (K16); *CDP (K16) *+CDP (K16) conditional jump, conditional call, interrupt, reset, etc. program control instructionsFor example:BCC P24, COND;CALLCC P24, cond, IDLE;INTR k5;reset;trap K5 Use the following directives or action modifiersFor example:Mmap (); Port (); <instruction> CR; <instruction> LrResource ConflictsC55X's resource operators use the following operators: Unit D ALU, the shifter of unit D, the exchanger of unit D, the exchanger of unit A, the Alu of unit A and the P unit address produce unit two data address (DA) generating unit, one coefficient address (CA) generating unit and one stack address (SA) generation order The unit bus can only be generated with a given number of data addresses two data read (DR) bus, a factor read (CA) bus, two data write (DW) bus, 1 ACB bus (the contents of the D unit registers to the Unit A and P units), A KAB bus (immediately count bus) and a KDB bus (immediate count bus) can only use a given number of busessoft-double parallel conditionsTwo memory operands must be a dual-ar indirection mode instruction cannot contain high_byte (SMEM) and Low_byte (SMEM) instructions cannot read, write the same memory cell if the K4 value in the instruction is 0~8, the value of the XDP is changed, so you cannot match the load DP The instruction consists of a parallel instruction read repeat Count Register (RPTC) instruction which cannot be composed with any one of the following single repetitive instructions

The 2 c55x instruction set can be divided into 6 types by operation type: Note: The attribute of an instruction includes: instruction, performing operation, whether to have and exercise the ability bit, length, cycle, the execution stage in the pipelining and the function unit of execution . Arithmetic Operation instruction bit Operation instruction Extended Auxiliary Register operation instruction Logical Operation Instruction Move Instruction Program Control Instructions