is in the process of learning SV, run the book on the examples, encountered problems.
function: The function returns an array.
Code1:
/ * Examples provided in the book, there are errors, not running
function void init (ref int f[5], int start);//main function definition without declaring automatic property
foreach (f)
F= i + start;
Endfunction
Initial begin
int fa[5];
FA = init (fa,5);
foreach (FA)
$display ("fa[%0d] =%0d", I, FA);
End
*/
#-----------------------------------------------------------------------------------
Code2:
The following code will run successfully under Modelsim. (Automatic is added when defining function)
Module Enum_name;
int fa[5];
Initial begin
FA = init (FA, 5);
Init (FA, 5);
foreach (FA)
$display ("fa[%0d] =%0d", I, FA);
End
function automatic void init (ref int f[5], input int start);
foreach (f)//Initialize array
F= i + start;
Endfunction
Endmodule
#-----------------------------------------------------------------------------------
Question:
In the 16th chapter of LRM, the following structure is provided when explaining program results:
Code3:
ModuleTest (...)
intShared Variable shared by programs P1 and P1
ProgramP1;
...
Endprogram
Program p2;
...
Endprogram //P1 and P2 is implicitly instantiated once in module test
endmodule
to ask, how can the function of Code2 in the Program...endprogram inside, form the Code3 form of code structure.
among them, Code4 is I try to change, but in Modelsim compile can pass, but run times wrong.
Code4:
Module Enum_name;
int fa[5];
Initial begin
FA = init (FA, 5);
Test.init (FA, 5); The 61st line of the prompt in the corresponding error message
foreach (FA
$display ("fa[%0d") =%0d ", I, Fa end
//------------------------------------------------------------;
program automatic test;
function automatic void init (ref int f[5], input int start);
foreach (f)//initialize array
f = i + start;< BR style= "Word-wrap:break-word" > endfunction
endprogram< BR style= "Word-wrap:break-word" >endmodule
run the wrong content of the Times:
# Compile of ENUM_NAME.SV is successful with warnings.
Vsim-gui Work.enum_name
# Vsim-gui Work.enum_name
# Loading SV_STD.STD
# Loading Work.enum_name
# * * Error: (vsim-3927) D:/MODELSIM/SYSVERILOG/ENUM/ENUM_NAME.SV () Accessing program item '/enum_name/test/init ' From a Non-program design unit enum_name is illegal.
#
# region:/enum_name
# * * Error: (vsim-3927) D:/MODELSIM/SYSVERILOG/ENUM/ENUM_NAME.SV () Accessing program item '/enum_name/test/init ' From a Non-program design unit enum_name is illegal.
#
# region:/enum_name
# * * Error: (vsim-3927) D:/MODELSIM/SYSVERILOG/ENUM/ENUM_NAME.SV () Accessing program item '/enum_name/test/init ' From a Non-program design unit enum_name is illegal.
#
# region:/enum_name
# Error Loading Design
To solve!!! Compilation and operation of SystemVerilog in Modelsim
