Transplantation of Nucleus

 

Nucleus PLUS is the operating system kernel designed by ATI for embedded system applications with high real-time requirements. About 95% of the Nucleus PLUS code is written in ansi c language. Therefore, it is very easy to transplant and support most types of microprocessors, such as X86, 68 K, PowerPC, MIPS, and ARM.

After the cut-off compilation, the core code area of Nucleus PLus generally does not exceed 20 kb. It also provides TCP/IP network, graphic interface Grafix, File system and other modules. Another feature is that the source code is provided free of charge, which helps reduce development costs.

S3c2410A is a high-performance, low-power, 16/32-bit Proteus microcontroller developed by Samsung Based on ARM920T kernel. It integrates a wide range of system peripheral controllers. With the Nucleus PLUS operating system, you can easily develop applications suitable for handheld devices and various low-power products to accelerate the release of new products. Startup Process of NUcleus PLUS

The Startup Process of the embedded real-time operating system kernel Nucleus PLus is shown in 1. INT_Initialize initializes basic hardware such as the interrupt vector table, system stack, and clock interruption;

Operating system initialization (INC_Initialize) is mainly to complete the mailbox, queue, pipeline, semaphore, event set and other software components initialization; application initialization (Application_Initialize (first-available_memory )) it mainly initializes user-defined applications, such as creating a memory pool, creating tasks, creating semaphores, creating interruptions, and compiling user applications. During the porting process, you need to modify the part of the board-level initialization (INT_Initialize]), which is compiled by the ARM assembly language and described in detail below.

NLicleus PLUS porting process

INT-Reset subroutine Modification

INT-Reset is the program entry at the startup of the Nucleus PLUS, because according to the architecture of the ARM microprocessor, after the system hardware is powered on or Reset, the First Command executed by ARM is at the address 0x00000000, that is, the ARM Reset abnormal (Reset) vector address. Therefore, a jump command is placed at this address: BINT_Reset.

In the INT_Reset subroutine, the hardware initialization program is placed to complete two functions:

1. Change the operating Mode of ARM to the management Mode. The management Mode is a protection Mode that ARM provides to the operating system;

2. Disable FIQ and IRQ interruption because the interruption cannot be interrupted during system initialization. the interruption can be enabled only after the interruption service subprogram Initialization is complete, and then the interruption is responded.

INT_Reset

MRS R1.CPSR

BIC R1, R1, # MODE_MASK

ORR R1, R1, # SUP_MODE

ORR R1, R1, # LOCKOUT

MSR CPSR_cxsf, R1

Create an abnormal vector table and an interrupt vector table

According to the ARM architecture, ARM has seven types of exceptions, each of which has its own entry address, namely the Exception vector table (Exception Vectors ). The abnormal vector table is placed in a 32-byte continuous space starting from 0X00000000. There are 56 interrupt sources in S3C2410A, but some interrupt sources share a medium interrupt vector. Therefore, you only need to create an interrupt vector table containing 32 interrupt sources.

INT_Vectors

Ldr pc, INT_ReseLAddr

Ldr pc, INT_Undef_Addr

Ldr pc, INT_Software_Addr

Ldr pc, INT_Prefetch_Addr

Ldr pc. INT_Data_Addr

Ldr pc, INT_Reserved_Addr

Ldr pc, INTjRQ_Addr

Ldr pc, INT_FIQ_Addr

Configure the memory controller and MMU

Memory Manage Unit is short for Memory management units. It is used to map virtual addresses to actual physical addresses. It is part of ARM and has a small amount of storage space for matching tables from virtual addresses to physical addresses, that is, the switch side buffer (t l B s-T r a n s l a t I 0 nLookaside Buffers ). MMU implements two main functions: Converting virtual addresses into physical addresses and controlling the access and enabling of memory.

Configure the memory controller of the S3C2410A to initialize the peripheral memory of the S3C2410A target board. It mainly sets the memory type, bus width, and information, and focuses on setting the SDRAM, such as the number of column addresses and signal line time series.

Stack Initialization

C and ARM assembly source files are compiled through the ARM development environment ADS1.2 link. The generated Image files include RO (read-only code, Data Segment) and RW (read/write data segment) and ZI (the segment to be initialized as 0. When the image file is loaded into flash, the RO and RW segments are in the Flash position as shown in Figure 2 (a). IImage $ RO $ Basel is the start address of the RO segment, it is also the loading and execution address that contains the RO output segment, which can be set in ARM Linker, that is, the value of-r0-base, which is set to 0x00000000 when starting from flash, the ZI segment does not need to be loaded into flash.

After the hardware circuit is reset, the RW segment in the image file needs to be copied from Flash to the SDRAM, and the content of the ZI output segment needs to be initialized with "0, the position of the output segment in the storage area is shown in Figure 2 (B ). IImage $ RW $ Basel is the execution address that contains the RW output segment. This address value also needs to be set in ARM Linker, that is, the value of-rw-base, generally, the value of-rW-base is set to the address range of SDRAM. Here, the first address of s d r a m is set to 0x30000000. You need to write the code to complete the above operations during the process of Transplantation of Nucleus PLUS.

ARM has seven operating modes: user mode (usr), fast interrupt mode (fiq), external interrupt mode (irq), and management mode (svc) data Access stop mode (abt), system mode (sys), and undefined command stop mode (und ). During stack initialization, the stack should be set for each running mode of S3C2410A. Generally, the stack size can be set to 4 kb. In addition, you must set the starting address, size, and priority of the HISR (High-Level InterruptService Routines) stack. The stack size can be set to 2 kb.

Interrupt Initialization

1. copy the abnormal interrupt vector table of Nucleus PLUS from ROM to RAM, that is, copy the abnormal interrupt vector table with the address 0x00000000 to the address 0x33ffffff00, in this way, the abnormal interrupt vector table can be extracted from RAM during the interrupt response process to improve the response speed of the interrupt;

2. Disable the watchdog clock and create an interrupt vector table for all IRQ interruptions;

3. Clear the judgment bits of all interruptions.

System clock interruption Initialization

Because Timer4 is used as the system clock of the Nucleus PLUS, you must configure the clock Interruption During the transplantation of the embedded real-time operating system. The configuration process is as follows:

1. Set the interruption period of the Internal timer Fimert timer of S3C2410A to 10 ms;

2. Establish the interrupt vector of Timer4 and use the Timer4 clock as the cycle clock of the system of the Nucleus PLUS;

3. initialize the MPLL control register m p l c o n of S3C2410A and set the main clock FCLK of S3C2410A to 266 MHz;

4. Set the frequency divider register CLKDIVN to make HCLK = FCLK/2, PCLK = HCLK/2.

Set the first address of the system available storage Zone

After the Board-LEVEL initialization program (I N T-Initialize) is completed, the system starts to call the operating system initialization program (INC-Initialize ). In this case, you need to set the first-available-memory address of the memorY that can be used by users to make fiT St-available-memory = IImage $ bss $ zI $ LimitI, here, IImage $ bss $ ZI $ Limitl is the end address of the 0 Segment (ZI segment) initialized in the executable image file generated by the ARM linker. After modification, call the program INC_Initialize (VOID * first_available_memory) to initialize the operating system. The transplantation of Nucleus PLUS is also over.

Conclusion

This article describes in detail the transplantation process and method of Nucleus PLUS on S3C2410A. The transplanted code runs normally on the FS2410 Development Board of Shenzhen youlong Technology Co., Ltd, supports multi-task scheduling, inter-task communication, and interrupt response. Because the porting process is specific to a specific hardware environment, the ARM assembly language should be used during the transplantation, which is a difficult point for porting embedded operating systems. The focus of transplantation is to establish an interrupt vector table, create an OS clock interrupt, and set the system stack. The Transplantation method discussed in this article also has some reference value for the transplantation process of other embedded operating systems on ARM microprocessor.

 

Source: Nucleus transplantation (conversion) _ trembling in the mind _ Baidu Space