Transplantation Study Notes of dm9000 driver on mini2440

Dm9000Driver inMini2440Transplant Study Notes on

I want to know the principle of porting and modifying the dm9000, So I analyzed the timing diagram and pin connection.

First, let's take a look at the connection between the dm9000 pin and the mini2440 pin.

Dm9000 mini2440 Function Description
Sd0 data0 data signal
|
Sd15 data15 data signal
CMD addr2 identifies the address or data
Int eint7 interrupt
Ior # Noe READ command enabling
Iow # Nwe write command enabling
Aen ngcs4-chip selection

It can be seen that 16 data lines and 1 address line are connected, and the only address line is used to determine whether the data lines transmit addresses or data. Therefore, these 16 data lines are used for data and addresses.

The bank4 used by the chip selection signal activates the chip selection enabling signal ngcs4 when accessing the address in the range of 0x2000 0000-0x27ff FFFF.

In the kernel provided by mini2440, the address Io address of dm9000 is 0x2000 0000, and the data Io is 0x2000 0004.
Addr2 is not activated when writing data to the address Io, so the data sent to dm9000 is the address, and addr2 is activated when writing data to the data Io, therefore, the data transmitted to dm9000 is data.

Now let's look at the time series signals of dm9000 and S3C2440.

Write sequence of dm9000

The io16 and io32 pins are not connected at the mini2440, so the timing of these two pins is not checked.
As follows:

There is also the time needed to write the command to enable the next write command to enable at least 84ns, T6
Next is the write time sequence of S3C2440. Since dm9000 is connected to bank4, the write time sequence of the bank is as follows:

Since dm9000 only needs to enable chip selection and write command enabling and data signal on mini2440, we don't want to view ADDR and NBE signals.

What are these values ?~

Let's take a look at bankcon4.

Here, the values take the clock as the cycle, while bankcon is connected to the memory controller (Refer to Table 1-4 in the s3c2440a Data Manual ), memory Controller uses the hclk bus clock signal (refer to figure 7-1 in the s3c2440a Data Manual, thanks to Kasim). According to the S3C2440 manual, hclk is divided by fclk, the specific frequency division is different from that set for each board. Therefore, the frequency setting here should be analyzed based on the board settings. Assume that the frequency is 400 MHz, then fclk, hclk, the pclk division ratio is. Is hclk 200 MHz? Is every clock cycle 5ns?

Start to compare and compute the time sequence diagram of dm9000
TCOs corresponds to T1. Should it be at least 5ns, that is, 1 clock?
Tacc corresponds to T2. Should tacc be 22ns at least? We have to select at least 6 clock, that is, 30ns.
Toch corresponds to T5, which is not set here, but literally, I think tcoh is toch, and toch should be at least 5ns, that is, 1 clock.
Tcah corresponds to T4. Since toch already exists, can it be set to 0ns, that is, 0 clock?

In S3C2440, the interval between a write command and the next write command is toch + tcah + tacp + TACs + TCOs.
TACs is the start interval of the chip selection signal after the address signal. Here we set it to 0 NS, that is, 0 clock.

Toch + tcah + tacp + TACs + TCOs should be greater than 84
5 + 0 + tacp + 0 + 5> 84
Tacp> 74
However, the maximum tacp value is 6 clock, that is, 30ns, and 44ns is missing. About 9 clock
As long as toch tcah TACs and TCOs are modified, although we give minimum values, we can relax the range to ensure signal stability,
Set TCOs and toch to four clock
Set TACs and tcah to 2 clock
The total time is (4 + 2 + 6 + 2 + 4) * 5 = 90ns

The last dm9000 can only process one data in one cycle, so PMC should be normal (1 data)

The write time series analysis is complete. Now let's take a look at the read time series.

The read sequence of dm9000 is as follows:

As follows:

After the READ command is enabled, it takes at least 80 ns to enable the next read command. It is t6.
Next is the read time series of S3C2440, which is as follows:

As follows:

TCOs corresponds to T1, so it should be at least 5ns, that is, 1 clock. Here we set it to four clock which is the same as the write operation.
Tacc corresponds to T2, so it should be at least 22ns. Here, it is set to 6 clock with the same write operation.
When toch corresponds to T5, should it be at least 5ns, that is, one clock. Here we set it to four clock with the same write operation.

Set the same time interval as the write operation.
The tcah is composed of 2 clock
Tacp is 6 clock
TACs has 2 clock
PMC is normal (1 data)
Then, let's take a look at the time interval from the completion of the read command to the next read command enabling 80 ns not

Or toch + tcah + tacp + TACs + TCOs
(4 + 1 + 6 + 1 + 4) * 5 = 15*5 = 90ns, meeting the conditions

What about bankcon4? The settings are as follows:
TACs = 2 clock = 10
TCOs = 4 clock = 11
Tacc = 6 clock = 100
Tcoh = 4 clock = 11
Tcah = 2 clock = 10
Tacp = 6 clock = 11
PMC = normal (1 data) = 00

That is, 0x5cec

Let's look at bwscon. This register is responsible for configuring the bandwidth and waiting status of the bank.
We are connected to ngcs4. What about st4, ws4, and dw4?
Dw4 is described as the bandwidth of bank4. If dm9000 is connected to 16 address lines, the bandwidth is 16. Select 01 here.
The description of ws4 is bank4 waiting status. dm9000 is not connected to the wait pin, so this field can be ignored.
St4 is described as bank4 using UB/lb (write high/low byte enabling), dm9000 is not connected to the nwbe [] pin, so this field does not matter

Now let's take a look at the changes made by the dm9000 driver to adapt to the S3C2440 in a friendly Linux environment.

# If defined (config_arch_s3c2410) # Include <Mach/regs-mem.h> # Endif # If defined (config_arch_s3c2410) // Obtain the address of the bandwidth and Wait Status control register Unsigned int oldval_bwscon = * (volatile unsigned int *) s3c2410_bwscon; // Obtain the address of the control register of Bank 4 Unsigned int oldval_bankcon4 = * (volatile unsigned int *) s3c2410_bankcon4; # Endif # If defined (config_arch_s3c2410) // Clear dw4 on bwscon to 0 first // Set the bandwidth to 16 bits // Enable the Wait Status of bank4 // Enable the high/low byte write function of the SRAM of bank4. * (Volatile unsigned int *) s3c2410_bwscon) = (Oldval_bwscon &~ (3 <16) | s3c2410_bwscon_dw4_16 | s3c2410_bwscon_ws4 | s3c2410_bwscon_st4; // Set PMC-page mode configuration-1 Data // Tacp-page Mode Access cycle @ page mode-6 clocks // Tcah-address hold time after ngcsn-4 clocks // Tcoh-chip selection hold time after Noe-1 clock // Tacc-access cycle-14 clocks // TCOs-chip selection set-up time before Noe-4 clocks // TACs-address set-up time before ngcsn-0 clock * (Volatile unsigned int *) s3c2410_bankcon4) = 0x1f7c; # Endif # If defined (config_arch_s3c2410) Printk ("now use the default MAC address: 08: 90: 90: 90: 90: 90 \ n "); Mac_src = "friendly-arm "; Ndev-> dev_addr [0] = 0x08; Ndev-> dev_addr [1] = 0x90; Ndev-> dev_addr [2] = 0x90; Ndev-> dev_addr [3] = 0x90; Ndev-> dev_addr [4] = 0x90; Ndev-> dev_addr [5] = 0x90; # Else # If defined (config_arch_s3c2410) * (Volatile unsigned int *) s3c2410_bwscon = oldval_bwscon; * (Volatile unsigned int *) s3c2410_bankcon4 = oldval_bankcon4; # Endif

It mainly implements three functions.
Modify bwscon registers
Modify bankcon4 register
Modify Mac Information

In the past, we saw that uboot was transplanted to mini2440, fclk, hclk, and pclk.

The hclk on mini2440 is 100 MHz, that is, a 10 ns clock, which is exactly two times larger than the above analysis,

Then we can set the number of clocks/2.
TACs = 1 clock = 01
TCOs = 2 clock = 10
Tacc = 3 clock = 010
Tcoh = 2 clock = 10
Tcah = 1 clock = 01
Tacp = 3 clock = 01
PMC = normal (1 data) = 00

That is, 0x3294
It should be noted that when using wait signals, the tacc must be greater than or equal to four clock
Therefore
* (Volatile unsigned int *) s3c2410_bwscon) =
(Oldval_bwscon &~ (3 <16) | s3c2410_bwscon_dw4_16 | s3c2410_bwscon_ws4 | s3c2410_bwscon_st4;
* (Volatile unsigned int *) s3c2410_bankcon4) = 0x1f7c;

Change
* (Volatile unsigned int *) s3c2410_bwscon) =
(Oldval_bwscon &~ (3 <16 | s3c2410_bwscon_ws4 | s3c2410_bwscon_st4) | s3c2410_bwscon_dw4_16;
* (Volatile unsigned int *) s3c2410_bankcon4) = 0x3294;

You can also
# If defined (config_arch_s3c2410)
Printk ("now use the default MAC address: 08: 90: 90: 90: 90: 90 \ n ");
Change
# If defined (config_arch_no2410)
Printk ("now use the default MAC address: 08: 90: 90: 90: 90: 90 \ n ");

In this way, the MAC address is obtained by reading the dm9000. After the experiment, the MAC address obtained is FF: ff.
I don't know what impact it will have on the TCP/IP protocol stack.

This is used
* (Volatile unsigned int *) s3c2410_bwscon) =
(Oldval_bwscon &~ (3 <16) | s3c2410_bwscon_dw4_16 | s3c2410_bwscon_ws4 | s3c2410_bwscon_st4;
* (Volatile unsigned int *) s3c2410_bankcon4) = 0x1f7c;
Latency

The response time is around 0.747.

This is used
* (Volatile unsigned int *) s3c2410_bwscon) =
(Oldval_bwscon &~ (3 <16 | s3c2410_bwscon_ws4 | s3c2410_bwscon_st4) | s3c2410_bwscon_dw4_16;
* (Volatile unsigned int *) s3c2410_bankcon4) = 0x3294;
Latency

The response time has been improved ~ However, I don't have a probe, so I don't know if this setting will have a negative impact on dm9000 ~

So don't come to me if your dm9000 crashes ~ Hahaha (Escape ~

Since timing analysis is also the first attempt ~ So please note that something is wrong. Thank you very much = 3 = )/