Tri-State (tri-state, T/s, sustained tri-state or S/t/s) Gate Circuit

Tri-state, T/s , Sustained tri-state or S/t/s ) Signal door circuit

A three-state signal (Tri-State or t/s), which is different from a general gate circuit. In addition to high-level and low-level signals, the output end also has a third State, that is, the high-impedance state, also called the prohibited state, but not three logical value circuits. A device in these three States is called a three-state gate. Generally, the connection between a door and other circuits is nothing more than two States: 1 or 0. In a complicated system, in order to transmit signals of different components on a transmission line, the corresponding logic device is called a three-state gate. In addition to the two states, the three-state gate also has a high-impedance state, it is equivalent to the circuit connecting the door to it being disconnected. (Because it is impossible for you to disconnect it in the actual circuit, you can set such a State to make it disconnected ). A three-state gate is an output-level extension logic function and a control switch. It is mainly used for bus connection because the bus only allows one user at the same time. Generally, multiple devices are connected to the data bus. Each device is switched over through signals such as CS. If the device is not switched over, the device is in a high-impedance state, which is equivalent to not connected to the bus, other devices are not affected. Only devices that have been selected to obtain the right to use the bus can drive signals. devices that do not have the right to use the bus cannot drive signals. To prevent conflicts between devices on the bus, the devices connected to the bus must first set the output signal to three States, which is equivalent to disconnecting the bus to avoid conflicts with other devices on the bus. This output port is a three-state output port. Continuous three-state signal (Sustained tri-stateOrS/t/s, OrSTS)Is a low-level valid three-state signal. at a certain time, there may be only one device drive, A device whose signal is low must drive the signal to a high level and maintain at least one clock cycle before it releases control over the signal. The new device can drive the signal only after the device that originally owns the signal releases control of the signal.S/t/sThe signal needs to be pulled up so that no device is driving him, keep an invalid level, that is, high level. The pull-up resistance is provided by the master control device. Tri-state logic and non-gate shows the three-state logic and non-gate. This circuit is actually composed of two and non-gates with a diode D2 . The right half of the dotted line is a non-portal with an active discharge circuit. It is called the data transmission part. T5 management U I1 , U I2 is called the data input end. The left half of the dotted line is the state control part. It is a non-gate and its input C is called a control end, a license input end, or an enabling end.   When C Usually, T4 Output a high level T5 To make the right half of the dotted line in the working state. In this way, the circuit will Ui1 , Ui2 The received signal is sent to the output end,   Enable Uo It is either high or low. When C Usually, T4 Output low-level T5 , Make T6 , T7 , T10 Deadline. On the other hand D2 Set T8 The base pole potential clamp in 1 V Left and right, make T9 Deadline. Because T9 , T10 All ends, from the output end U0 Check that the circuit is in the high-impedance state. The logical symbols of the three-state logic and the non-gate are shown in the left figure below. Where (A) Graph RepresentationCHigh-power terminals are usually in the working state, which is called high-efficiency three-state and non-gate. (B) Graph RepresentationCThe end is a low-power working state, which is called a low-efficiency three-state and non-gate. Note the difference when using it. The most important use of the Three-State and non-gate is to send several sets of different data and control signals to one wire in turn, as shown on the right, which is widely used in computers. However, it should be pointed out that to ensure that many three-state gates connected to the same bus can work normally, one necessary condition is that at most one gate is in the Working State at any time, otherwise, several doors may be working at the same time, and the output status may be abnormal. Three-state output gate circuit (TS(Three-state output Gate) Door) The schematic diagram of the three-state gate output circuit. In the figure, if two inverters and a diode in the dotted box are cut off, the rest is typical.TTLAnd non-gate circuit. The so-called three States refer to the output end. . CommonTTLNon- Two Transistors at the gate output pole T4 , T5 Always keep one conduction mode and the other end push-pull mode. T4 Conduction, T5 End, output high level Y = 1 ; T4 Deadline, T5 Conduction, low output level, Y = 0 . In addition to the preceding two states, the three-state gate appears again. T4 , T5 The third state that ends at the same time. Because the transistor cutoff time C , E Between them is an infinite impedance, and the output end Y To the ground, to the power supply ( VCC ) The impedance is infinite. Therefore, the third State is also called the high-impedance state. Three statuses are analyzed: The control signal can beEnYou can alsoAdd: En=0, =1, ThenC = 0,VB1 = 0.9 V,Vc2=0.9 V vb4 = vc2 = 0.9 V , t4 deadline ( t4 conduction potential vb4> 1.4 V ) VB1 = 0.9 V , T5 deadline, output end Y is high-impedance. En=1,=0,C = 1, The other twoA,BThere is no impact on the input, and it is a normal and non-gate circuit. When A = B = 1 , Then T2 , T5 Conduction, Vc2 = 1.0 V (Previously analyzed ). Diode D At the end of the phase (because of its anode voltage) Vc2 = 1.0 V , Less than Cathode C Point potential VIH = 3.4 V ), Does not work in the circuit. If A , B One of them is 0 , Then T2 , T5 As of now Vc2 = VIH + 0.7 = 4.1 V , Sufficient guarantee T4 Conduction, when En = 1 (   = 0 ), Diode D Does not work in the circuit, the circuit maintains the complete and non-gate logic functions. The three-state gate logical symbols are as follows: En=1, =0, En=0,YHigh Impedance=1,YHigh Impedance