Trigger a TTL circuit from ECL levels

ecl circuits typically has relatively small logic spans of approximately of MV. Because of the small span, to-drive TTL circuits from ECL levels normally entails the use of level converters, such as the MC10125, or comparators. Such circuits is relatively power-hungry and expensive. However, they is sometimes simply unnecessary. The circuit in figure 1 allows-trigger some TTL circuitry by generating a fairly short negative-going pul Se from the trailing edge of the ECL signal. The main requirement for the circuit to work are that the rate of ECL signal are in the tens of kilohertz. Such signals sometimes appear at the rear panels of some older types of measurement equipment. Such equipment can include sampling oscilloscopes or Time-domain reflectometers, Such as the 7s12 or 7s14 from Tektronix. In a measurement setup, the circuit in figure 1 exploits the sampling gate from a 7S12 plug-in unit.

Figure 2 shows the waveforms associated with the circuit in figure 1. The positive portion of the ECL signal charges capacitor C_{1 through the Schottky diode, D1. In this part of the operating cycle, transistor Q2 are off, and the output voltage is approximately 5V. On the negative-going edge of the driving pulse, the charge from coupling capacitor C1 causes the Base-emitter junctio N of Q2 to conduct, driving the transistor into saturation. The output voltage assumes a level slightly below 0V. The duration of the generated negative-going pulse depends on the speed with which C2discharges. The discharge takes place through the base-emitter junctions of Q1 and q2and resistor R1. The duration is difficult to calculate, but for a rough estimate, you can use the following equation: /c4>}

WHEREΔV≈0.8V is the ECL span, V_{DS≈0.15V is the voltage drop of the Schottky diode, and Vbe≈0.6v is the voltage drop of the base-emitter junctions. In practice, the durations is shorter than predicted because the equation does not take account of the Base-emitter resis Tances of Q1 and Q2. For the 1, the duration is approximately 2µsec. The crucial component in the circuit are D1, which must be a Schottky type, because of the voltage swing of the ECL sig NAL, which is nearly the same as the base-emitter voltage of the conducting silicon transistor. Proper operation of the circuit occurs because of the voltage difference between Schottky and silicon-junction levels, WHI CH is typically 0.1 to 0.3V. This difference allows for the strong saturation of Q2 just after the trailing edge of the ECL signal.}

Trigger a TTL circuit from ECL levels