UART sub-frequency lock register divisor latches register

• Frequency lock register (urdlm and urdll)

Urrbr, urthr, and urdll share the same address.When the dlab bit of the urlcr register is 1All accesses to the shared address are urdll; when the dlab bit of the urlcr register is 0, the read operation on the shared address will access urrbr (receiver er buffer register), and the write operation on the shared address will access urthr (transmitter holding register ).

Urier and urdlm share the same address. When the dlab bit of the urlcr register is 1, All accesses to the shared address are urdlm; when the dlab bit of the urlcr register is 0, all accesses to the shared address are urier (Interrupt enable register );

In addition, urdlm and urdll have their own exclusive addresses. If you use their exclusive addresses, You can reset the dlab bit of the urlcr register so that the shared address points to urrbr by default, urthr and urier registers.

The structures of urdlm and urdll are as follows: