Uclinux-2008r1-rc8 (bf561) to VDSP5 Transplant (a): The Trouble with the PLL

There's a very strange question:

After the DSP on the power directly on the emulator running Uclinux kernel, the serial port can not receive normal output, only one or two abnormal characters. But with VDSP4.5 run the original write a serial program, you can normally output.

The first depressing problem is that the serial port program runs through it again, and then how to run the Uclinux kernel is ok (unless power is lost). The uart_*-related register configuration for comparing the two programs is identical after interruption. Moreover, before and after the operation of the Uclinux two times, the program has no changes, it should have no relationship with the configuration. Comparison of the PLL configuration is exactly the same (27M crystal oscillator, 594M cclk,99m sclk).

The second depressing problem is that if you compile the uclinux kernel into a LDR file and burn it to flash, there is no problem.

The reason for this is that there is a section of code in the Head.s that sets the PLL:

r0 = CONFIG_VCO_MULT & 63;　　/* Load the VCO multiplier　　　　　　　　 */
r0 = r0 << 9;　　　　　　　　　　/* Shift it over,　　　　　　　　　　　　　　　　　 */
r1 = CLKIN_HALF;　　　　　　　　/* Do we need to divide CLKIN by 2?*/
r0 = r1 | r0;
r1 = PLL_BYPASS;　　　　　　　　/* Bypass the PLL?　　　　　　　　　　　　　　　　 */
r1 = r1 << 8;　　　　　　　　　　/* Shift it over　　　　　　　　　　　　　　　　　　 */
r0 = r1 | r0;　　　　　　　　　　/* add them all together　　　　　　　　　　 */

p0.h = hi(PLL_CTL);
p0.l = lo(PLL_CTL);　　　　　　/* Load the address　　　　　　　　　　　　　　　 */
cli r2;　　　　　　　　　　　　　/* Disable interrupts　　　　　　　　　　　　　 */
ssync;
w[p0] = r0.l;　　　　　　　　　/* Set the value　　　　　　　　　　　　　　　　　　 */
ssync;
idle;　　　　　　　　　　　　　/* Wait for the PLL to stablize　　　 */
sti r2;　　　　　　　　　　　　/* Enable interrupts　　　　　　　　　　　　　　 */

When the program is running here, the PLL settings do not really work, although the value of the register has changed.

There is a note in the VDSP manual:

Note:in order to program the PLL, both cores must is in a idled state. Alternatively, it is acceptable as core B to being in the ' SRAM init ' state ' it enters after processor reset. For more information about this state, refer to "booting Methods" on another page.

In the VDSP environment, B core is actually in the Fullon state, and when the PLL is set, the B core is not running or is in the idle state.

The original serial port program is two cores are used. After you run it correctly, it doesn't matter if the following PLL settings don't work.

After burning to Flash, b core does not run, so the PLL settings are also successful!

Knowing the reason is easy to solve:

When running under the emulator, adding a idle instruction to the B core and running it prior to a core can fix the problem.

Ha ha!