In digital circuits, high voltage and low level are divided into 1 and 0, respectively. The pin of a digital circuit always has a level, either high or low, or 1 to 0 (in fact, there is another State, which will be mentioned later ).
In an embedded system, there must be a processor chip. In addition, there are other chips as external devices (peripherals). These chips work together with the processor to implement product functions. Complex products are often composed of a large number of chips. What is inevitable is that we need to connect all the peripherals to the processor. The simplest thing is to connect all the peripherals to the processor using independent (note that they are independent) signal lines, this is easy to understand, but the problem is: not feasible. Because the processor chip needs to lead to too many lines, from the perspective of chip production and product production, it is not practical. In addition, the processor (Here we assume that the processor is single-core rather than multi-core) processes transactions in a micro-serial manner, that is to say, if you want to perform read and write operations on peripherals at a certain time point, it can only be one of a large number of peripherals, that is, multiple peripherals cannot be simultaneously accessed by the processor at the micro level. Note that the microscopic concept is proposed here to distinguish it from the macroscopic one. In a macro sense, a processor can run multiple tasks simultaneously, however, these tasks run one by one at a micro level (Serial descriptions will be used later to describe "one by one "), the implementation of multi-task serial operation is realized by the operating system playing an important role. Back to our topic, it is impossible to connect each peripheral to the processor using an independent signal line, and the processor will only access one peripheral within a single time, can we use a shared signal line to connect all the chips together? This is the origin of the concept of bus. In layman's terms, if we have ten families around us, we do not need to create a separate article for each of the ten families to communicate with each other) (in this case, 45 roads need to be built), but a road can be built, and every home is connected to the road.
For the bus, we often say that the bus is processor, while other peripherals are mounted on the bus. There is a problem that we can only access one peripheral mounted on the bus at a time. How can we differentiate these peripherals? Like our path, we need to use addresses to differentiate every home. On the bus, addresses are also used to differentiate. In this way, the bus is divided into two types based on its functions. The first type is the address bus. The data on this bus will only flow from the processor to the peripherals, Which is unidirectional. Another type is the data bus, which is used to transmit data from the processor to peripherals (from the processor's perspective, it is a write operation) or transmit data from peripherals to the processor (read operations from the processor perspective). Obviously, the Data Bus is bidirectional. That is to say, in our embedded system, both the address bus and the Data Bus connect all chips that need to communicate with the processor.
The bus is wide. Just as our road is divided into "three lanes" or "four lanes", we say a 32-bit processor means that its data bus width is 32 bits, that is, "32 cars can run at the same time." Obviously, the wider the width, the faster our processor is, because we can access data faster from peripheral chips, this is why our computer is evolving to 64-bit. Similarly, the address bus also has a width. For 32-bit processors, the maximum width is 32-bit.
The concept of the bus is there, so the next question is, even if every peripheral has an address, where can this address be recorded? Is it on a peripheral chip? In this case, there is a problem where the addresses of each type of peripherals must not overlap. When two identical chips are required in a product, the addresses of the two chips cannot be distinguished. It seems that there is a problem with this operation. In addition, if this is the case, each peripheral must be completely connected to (for example, 32) Data Bus and listen to data lines to see if the processor is "calling" itself. This is very complicated. In addition, the address may also be used up due to the increase in the number of peripherals. In general, the address cannot be stored on the peripheral chip. How can we let the peripherals know that the address is changed by the processor and requires read/write access? The answer is chip selection (CS,
Chip select) signal, or enable signal.
The chip selection signal is a (and also a) Notification signal for the peripheral chip, telling the chip "Hey, open the door, I want to bring something in or take something ", here we can only use data, not corn beam. Where can I find this signal source? Obviously, it can only come from the processor. Is it like a bus that every chip is connected together with a single line? In this case, all chips of the processor "One is open the door" open the door. If data is written by a processor, all chips may be written to the same data. When getting data, each peripheral chip will "throw" data, which will inevitably cause a Data Bus conflict, because some chips "throw" 1 to the bus, some are "throw" 0. In this case, the processor will be "crazy" because it does not know whether to get 1 or 0.
In this case, we obviously cannot connect all the chip selection signals. The chip selection signals can only be independent of each chip. As mentioned above, we use an address line to connect a peripheral chip? Or use other methods. If you use an address line to connect to a peripheral chip, you may have to mount up to 32 chips. This is obviously not the case. In reality, 32-bit numbers are used to represent the address of a peripheral chip. For example, 1 can represent chip A, and 6534 can represent another chip B. From this point of view, in theory, we can represent a 32-power (4294967296) device of 2. In theory, this is because some devices occupy a large amount of addresses. Now, there is another problem. What if we convert a 32-bit address bus into a chip signal? This requires the introduction of the decoder concept.
A decoder converts a data signal into a signal on a signal line. For example, a 3/8 decoder can convert a data with a bandwidth of three to eight completely independent signal lines (power-3 of 2, when the binary 011 is written to the data side, it corresponds to 3rd of the 8 lines. When the binary 111 is input, it corresponds to the last of the 8 lines. With the decoder, the processor's address line is simplified. As long as 32 IP lines are added with an external decoder, a large number of peripheral chips can be accessed. We have solved the problem of selecting external devices. Now we have to look back at the data bus.
Figure 1 3/8 Decoder
In an embedded system, the data bus of all chips can be understood as directly connected. The word "understandable" is used because the bus driver is added to improve the load capacity of the bus. To understand, let's take a look at the tap water in our lives. For example, in Beijing, theoretically, all the water pipes may be connected together, but in the middle, it may be necessary to increase the water pressure, there are many small water stations used to increase water supply pressure, and it is impossible for all the tap water in Beijing to come from a water plant. Even if all the data buses are connected together, there may be problems. When writing data to an external device, the processor first transmits the address of the target peripheral to the address bus, and the address decoder converts the address decoder into a chip selection signal of a signal and sends it to the target peripheral, after receiving this signal, the target peripherals open the door. Next, the processor will transmit the data to the peripherals to the data bus. Because only the target peripheral chip opens the "door", the data will only enter the target peripherals, other peripherals will not receive anything. Good! There should be no problem in writing data to the processor. Let's take a look at it. Since data is transmitted from peripherals to processors, although we use the same method as writing to open the "door" of the target peripherals, at this time, other peripherals are also on the data bus. They may be at 1 or 0. Will this affect the processor's reading of the data from the target peripherals? Of course not, but we have to introduce another concept: high-impedance.
---- High-impedance ModeObviously, when the processor reads data from the target peripherals, we hope that the data bus of other chips that are not selected will not affect the data transmitted by the target peripherals. What should we do? In fact, when the chip is not selected, its data bus is in a high-impedance state. The so-called high-impedance state can be understood as the PIN is disconnected inside the peripheral chip. As a result, it obviously does not affect the processor to read data from the target peripherals. We say that when a chip is not selected or is not enabled, its data bus must be in a high-impedance state. In the past, we used the opening and closing of the "door" as an example. What does the "door" mean? It refers to the peripheral data bus. The function of chip selection signal is to control the connection or disconnection between the peripheral data bus and the processor data bus. For more information about the high-impedance mode, see the previous article "high-impedance mode and three-state gate".
---- DriverIf the data on the bus is put on, we can say who is the driver at that time. That is to say, when the processor writes data to the peripherals, it is driving the data bus, while when the processor reads data from the target peripherals, the target peripherals are driving the data bus. For the address bus, because it can only be written from the processor to the target peripherals, the address bus will always be driven by the processor. When a chip is not selected, we say it does not drive the data bus.
---- Three-state gateWe have mentioned that the data bus of the peripheral chip is in the high-impedance state when it is not selected. When it is selected, its level may be high (1) or low (0 ). In this way, we say that the chip pins of the peripheral data bus belong to three States: high level, low voltage, and high impedance. For more information about the three-state gate, see the previous article "high-impedance and three-state gate".
---- Level Validity
We have learned about the chip selection signal and the three-state gate. We need to point out that the chip selection signal is usually not a three-state gate, and there are only two States, that is, high level or low level. As we mentioned above, the chip selection signal is used to "Open the door", and the chip selection signal has a high and a low level. Is it a high level that means "Open the door? Or low? For this problem, we say that if a level is "Open" for a chip selection signal, it is the effective level of the signal. For example, for a chip selection signal, if the low level indicates "Open the door", then we say this chip selection signal is effective at a low level. Although we use the chip selection signal to explain the effectiveness of the level, many signals have validity issues. For example, the reading and writing signals we will discuss later have validity issues.
---- Timing sequence we mentioned earlier that when the processor wants to write data to the peripheral chip, it needs to first put the address of the peripheral to be accessed on the address bus. Then, the decoder converts the data on the address bus into a chip selection signal, and the chip selection signal enables the target peripheral chip. Next, the processor writes the data to the Data Bus to complete a write operation. Obviously, data on the address line must be retained for a period of time before the processor writes data to the data bus. Otherwise, the decoder cannot make the chip selection signal valid for a long time. After writing data, the processor does not need to ensure that the address on the address bus is valid. We can see that these operations have a strict chronological order, which is called time series. Time Series describes the interaction signals between the processor and external devices.
"Procedure": only by following this "procedure" can we ensure normal communication between the processor and external devices. This is like the traffic lights on our roads. If our pedestrians and vehicles do not follow the instructions, an accident will occur. Generally, a time sequence diagram is used to describe the signal "procedure" for communication between chips ".
Figure 2 read sequence diagram
Figure 3 read sequence diagram
We can see that address indicates the address bus, DQ indicates the data bus, Ce indicates the chip selection signal, and is effective at a low level, its width must always be valid during read operations. Learning to view the sequence diagram is very helpful for embedded system development, because we have to deal with chips. In the time sequence diagram, a lot of time requirement information is usually identified. When writing the startup code, you need to initialize the chip address register and read/write sequence of each address space. The timing configuration is based on the time requirement of the peripheral chip, which is an important part of the chip manual. When multiple peripheral chips exist in an address space, we need to consider the time requirements of the slowest peripheral chip. Otherwise, some chips will not work properly.
---- Reading Signal
When the processor needs to read signals from the peripheral chip, in addition to generating the chip selection number, it also needs to tell the peripheral chip that this is a read operation, not a write operation, which is achieved through the reading signal.
---- Write SignalI have talked about reading signals. I think it is not difficult to understand writing signals. This signal is used to tell the peripheral chip that it is an operation to write data to the peripheral chip.
---- I/O Ports previously mentioned peripherals (CHIPS). Now it is time to classify peripherals. Generally, there are two types of peripherals: Memory peripherals and non-memory peripherals. The latter is often called an I/O device. Here I/O is short for input/output, that is, input and output. It can be seen that I/O peripherals are a very broad concept. Memory peripherals are characterized by sequential space. For example, the SDRAM memory is a memory peripheral. If the memory size is 8 Mb, the occupied address space will also be 8 Mb. Unlike memory peripherals, I/O peripherals generally use very few addresses. For example, an I/O peripheral may have multiple control registers. These control registers are multiple I/O Ports (addresses) in the processor ), writing data to this address is to write data to the Register corresponding to the peripherals, and vice versa, it can also be reading. For example, a serial chip may have multiple registers, one is used to query the chip status, the other is used to set the chip function, and the other is used to read the data received by the chip from the serial line. Finally, another one is used to write data to the chip to send data online to the serial port. The registers of this serial port chip are independent I/O ports from the processor perspective.
I/O ports have read and write problems. Some ports are read-only, some ports are write-only, and some ports can be read or written, the read/write performance is determined by the registers of the peripheral chip, which can be found in the chip data manual. It should be noted that some memory peripherals also have I/O ports to control them. According to the name of the I/O port, an interface for the processor to read data from the outside or output data to the outside is a general term.
---- Interruption is a signal line that can generate high and low levels from the hardware point of view, but it must be understood from the processor point of view. As we have said, from a micro perspective, the work done by the processor is performed in order, and its processing of the program can only be the execution of one instruction and one instruction. If you need to access the peripheral chip, and it is possible that after the processor sends a read or write command, the peripherals are usually much slower than the processor, therefore, it takes some time for the peripheral chip to prepare the required data. In this case, if the processor waits until the output data of the peripheral chip executes Subsequent commands, it will take precious time and the time can be used for other work. Don't forget, from a macro perspective, the processor is often multitasking, and the task is the scheduling unit provided by the operating system. When a task is blocked by waiting for data from the peripheral chip, we can switch to another task to improve processing efficiency. This is a problem. When the processor processes another task, what if the data on the peripheral chip is good? Right! It is through the interrupt signal. The high and low levels of Interrupt signals can be used to indicate whether there is an interruption and the processor needs to pay attention to it to handle specific events (for example, events that have been prepared for peripheral data ).
From this point of view, the introduction of interruptions can greatly improve the processing efficiency. In order to use the interrupt on the processor, We need to initialize the interrupt controller of the processor at the beginning, such as installing the necessary interrupt service program or calling it ISR (interrupt service routine). Then, enable the interrupt shielding bit. The following operations must be performed in the interrupted service program:
---- In the development of embedded systems, we need to deal with peripheral chips. When debugging the driver, in addition to fully understanding the data manual of the chip, and in the process of software height, we also need to check whether the expected signal level occurs on the chip. For example, when writing a driver, we need to write an I/O port to operate the peripheral chip. When writing the corresponding I/O port, we know that the chip selection signal of the corresponding chip should be effective. Sometimes, we need to verify whether it happened as expected, which requires an oscilloscope. Generally, an oscilloscope can observe the signal state of two signal lines at the same time. The oscilloscope provides certain functions, such as signal capturing. One of the most important parameters of an oscilloscope is its collection frequency. According to the nycept theorem, if we want to use an oscilloscope to view signals with a frequency of M Hz, therefore, the sampling frequency must be at least two times, namely, M Hz. Someone may ask: why not use a multimeter? Because the acquisition frequency of the multimeter is very low, the rapid signal changes cannot be collected.
---- The logical analyzer is simply an oscilloscope with many signal channels. Through the logic analyzer, we can see the data on the address bus and the data bus. The logical analyzer provides certain programming capabilities for programming when to start to collect data on the bus. Reproduced in: Ghost is used for embedded system development and often has access to hardware. Embedded development requires a certain understanding of digital circuits and analog circuits. In this way, in-depth research can be conducted. Next we will briefly introduce some hardware-related concepts in embedded development.
In digital circuits, high voltage and low level are divided into 1 and 0, respectively. The pin of a digital circuit always has a level, either high or low, or 1 to 0 (in fact, there is another State, which will be mentioned later ).
In an embedded system, there must be a processor chip. In addition, there are other chips as external devices (peripherals). These chips work together with the processor to implement product functions. Complex products are often composed of a large number of chips. What is inevitable is that we need to connect all the peripherals to the processor. The simplest thing is to connect all the peripherals to the processor using independent (note that they are independent) signal lines, this is easy to understand, but the problem is: not feasible. Because the processor chip needs to lead to too many lines, from the perspective of chip production and product production, it is not practical. In addition, the processor (Here we assume that the processor is single-core rather than multi-core) processes transactions in a micro-serial manner, that is to say, if you want to perform read and write operations on peripherals at a certain time point, it can only be one of a large number of peripherals, that is, multiple peripherals cannot be simultaneously accessed by the processor at the micro level. Note that the microscopic concept is proposed here to distinguish it from the macroscopic one. In a macro sense, a processor can run multiple tasks simultaneously, however, these tasks run one by one at a micro level (Serial descriptions will be used later to describe "one by one "), the implementation of multi-task serial operation is realized by the operating system playing an important role. Back to our topic, it is impossible to connect each peripheral to the processor using an independent signal line, and the processor will only access one peripheral within a single time, can we use a shared signal line to connect all the chips together? This is the origin of the concept of bus. In layman's terms, if we have ten families around us, we do not need to create a separate article for each of the ten families to communicate with each other) (in this case, 45 roads need to be built), but a road can be built, and every home is connected to the road.
For the bus, we often say that the bus is processor, while other peripherals are mounted on the bus. There is a problem that we can only access one peripheral mounted on the bus at a time. How can we differentiate these peripherals? Like our path, we need to use addresses to differentiate every home. On the bus, addresses are also used to differentiate. In this way, the bus is divided into two types based on its functions. The first type is the address bus. The data on this bus will only flow from the processor to the peripherals, Which is unidirectional. Another type is the data bus, which is used to transmit data from the processor to peripherals (from the processor's perspective, it is a write operation) or transmit data from peripherals to the processor (read operations from the processor perspective). Obviously, the Data Bus is bidirectional. That is to say, in our embedded system, both the address bus and the Data Bus connect all chips that need to communicate with the processor.
The bus is wide. Just as our road is divided into "three lanes" or "four lanes", we say a 32-bit processor means that its data bus width is 32 bits, that is, "32 cars can run at the same time." Obviously, the wider the width, the faster our processor is, because we can access data faster from peripheral chips, this is why our computer is evolving to 64-bit. Similarly, the address bus also has a width. For 32-bit processors, the maximum width is 32-bit.
The concept of the bus is there, so the next question is, even if every peripheral has an address, where can this address be recorded? Is it on a peripheral chip? In this case, there is a problem where the addresses of each type of peripherals must not overlap. When two identical chips are required in a product, the addresses of the two chips cannot be distinguished. It seems that there is a problem with this operation. In addition, if this is the case, each peripheral must be completely connected to (for example, 32) Data Bus and listen to data lines to see if the processor is "calling" itself. This is very complicated. In addition, the address may also be used up due to the increase in the number of peripherals. In general, the address cannot be stored on the peripheral chip. How can we let the peripherals know that the address is changed by the processor and requires read/write access? The answer is chip selection (CS,
Chip select) signal, or enable signal.
The chip selection signal is a (and also a) Notification signal for the peripheral chip, telling the chip "Hey, open the door, I want to bring something in or take something ", here we can only use data, not corn beam. Where can I find this signal source? Obviously, it can only come from the processor. Is it like a bus that every chip is connected together with a single line? In this case, all chips of the processor "One is open the door" open the door. If data is written by a processor, all chips may be written to the same data. When getting data, each peripheral chip will "throw" data, which will inevitably cause a Data Bus conflict, because some chips "throw" 1 to the bus, some are "throw" 0. In this case, the processor will be "crazy" because it does not know whether to get 1 or 0.
In this case, we obviously cannot connect all the chip selection signals. The chip selection signals can only be independent of each chip. As mentioned above, we use an address line to connect a peripheral chip? Or use other methods. If you use an address line to connect to a peripheral chip, you may have to mount up to 32 chips. This is obviously not the case. In reality, 32-bit numbers are used to represent the address of a peripheral chip. For example, 1 can represent chip A, and 6534 can represent another chip B. From this point of view, in theory, we can represent a 32-power (4294967296) device of 2. In theory, this is because some devices occupy a large amount of addresses. Now, there is another problem. What if we convert a 32-bit address bus into a chip signal? This requires the introduction of the decoder concept.
A decoder converts a data signal into a signal on a signal line. For example, a 3/8 decoder can convert a data with a bandwidth of three to eight completely independent signal lines (power-3 of 2, when the binary 011 is written to the data side, it corresponds to 3rd of the 8 lines. When the binary 111 is input, it corresponds to the last of the 8 lines. With the decoder, the processor's address line is simplified. As long as 32 IP lines are added with an external decoder, a large number of peripheral chips can be accessed. We have solved the problem of selecting external devices. Now we have to look back at the data bus.
Figure 1 3/8 Decoder
In an embedded system, the data bus of all chips can be understood as directly connected. The word "understandable" is used because the bus driver is added to improve the load capacity of the bus. To understand, let's take a look at the tap water in our lives. For example, in Beijing, theoretically, all the water pipes may be connected together, but in the middle, it may be necessary to increase the water pressure, there are many small water stations used to increase water supply pressure, and it is impossible for all the tap water in Beijing to come from a water plant. Even if all the data buses are connected together, there may be problems. When writing data to an external device, the processor first transmits the address of the target peripheral to the address bus, and the address decoder converts the address decoder into a chip selection signal of a signal and sends it to the target peripheral, after receiving this signal, the target peripherals open the door. Next, the processor will transmit the data to the peripherals to the data bus. Because only the target peripheral chip opens the "door", the data will only enter the target peripherals, other peripherals will not receive anything. Good! There should be no problem in writing data to the processor. Let's take a look at it. Since data is transmitted from peripherals to processors, although we use the same method as writing to open the "door" of the target peripherals, at this time, other peripherals are also on the data bus. They may be at 1 or 0. Will this affect the processor's reading of the data from the target peripherals? Of course not, but we have to introduce another concept: high-impedance.
---- High-impedance ModeObviously, when the processor reads data from the target peripherals, we hope that the data bus of other chips that are not selected will not affect the data transmitted by the target peripherals. What should we do? In fact, when the chip is not selected, its data bus is in a high-impedance state. The so-called high-impedance state can be understood as the PIN is disconnected inside the peripheral chip. As a result, it obviously does not affect the processor to read data from the target peripherals. We say that when a chip is not selected or is not enabled, its data bus must be in a high-impedance state. In the past, we used the opening and closing of the "door" as an example. What does the "door" mean? It refers to the peripheral data bus. The function of chip selection signal is to control the connection or disconnection between the peripheral data bus and the processor data bus. For more information about the high-impedance mode, see the previous article "high-impedance mode and three-state gate".
---- DriverIf the data on the bus is put on, we can say who is the driver at that time. That is to say, when the processor writes data to the peripherals, it is driving the data bus, while when the processor reads data from the target peripherals, the target peripherals are driving the data bus. For the address bus, because it can only be written from the processor to the target peripherals, the address bus will always be driven by the processor. When a chip is not selected, we say it does not drive the data bus.
---- Three-state gateWe have mentioned that the data bus of the peripheral chip is in the high-impedance state when it is not selected. When it is selected, its level may be high (1) or low (0 ). In this way, we say that the chip pins of the peripheral data bus belong to three States: high level, low voltage, and high impedance. For more information about the three-state gate, see the previous article "high-impedance and three-state gate".
---- Level Validity
We have learned about the chip selection signal and the three-state gate. We need to point out that the chip selection signal is usually not a three-state gate, and there are only two States, that is, high level or low level. As we mentioned above, the chip selection signal is used to "Open the door", and the chip selection signal has a high and a low level. Is it a high level that means "Open the door? Or low? For this problem, we say that if a level is "Open" for a chip selection signal, it is the effective level of the signal. For example, for a chip selection signal, if the low level indicates "Open the door", then we say this chip selection signal is effective at a low level. Although we use the chip selection signal to explain the effectiveness of the level, many signals have validity issues. For example, the reading and writing signals we will discuss later have validity issues.
---- Timing sequence we mentioned earlier that when the processor wants to write data to the peripheral chip, it needs to first put the address of the peripheral to be accessed on the address bus. Then, the decoder converts the data on the address bus into a chip selection signal, and the chip selection signal enables the target peripheral chip. Next, the processor writes the data to the Data Bus to complete a write operation. Obviously, data on the address line must be retained for a period of time before the processor writes data to the data bus. Otherwise, the decoder cannot make the chip selection signal valid for a long time. After writing data, the processor does not need to ensure that the address on the address bus is valid. We can see that these operations have a strict chronological order, which is called time series. Time Series describes the interaction signals between the processor and external devices.
"Procedure": only by following this "procedure" can we ensure normal communication between the processor and external devices. This is like the traffic lights on our roads. If our pedestrians and vehicles do not follow the instructions, an accident will occur. Generally, a time sequence diagram is used to describe the signal "procedure" for communication between chips ".
Figure 2 read sequence diagram
Figure 3 read sequence diagram
We can see that address indicates the address bus, DQ indicates the data bus, Ce indicates the chip selection signal, and is effective at a low level, its width must always be valid during read operations. Learning to view the sequence diagram is very helpful for embedded system development, because we have to deal with chips. In the time sequence diagram, a lot of time requirement information is usually identified. When writing the startup code, you need to initialize the chip address register and read/write sequence of each address space. The timing configuration is based on the time requirement of the peripheral chip, which is an important part of the chip manual. When multiple peripheral chips exist in an address space, we need to consider the time requirements of the slowest peripheral chip. Otherwise, some chips will not work properly.
---- Reading Signal
When the processor needs to read signals from the peripheral chip, in addition to generating the chip selection number, it also needs to tell the peripheral chip that this is a read operation, not a write operation, which is achieved through the reading signal.
---- Write SignalI have talked about reading signals. I think it is not difficult to understand writing signals. This signal is used to tell the peripheral chip that it is an operation to write data to the peripheral chip.
---- I/O Ports previously mentioned peripherals (CHIPS). Now it is time to classify peripherals. Generally, there are two types of peripherals: Memory peripherals and non-memory peripherals. The latter is often called an I/O device. Here I/O is short for input/output, that is, input and output. It can be seen that I/O peripherals are a very broad concept. Memory peripherals are characterized by sequential space. For example, the SDRAM memory is a memory peripheral. If the memory size is 8 Mb, the occupied address space will also be 8 Mb. Unlike memory peripherals, I/O peripherals generally use very few addresses. For example, an I/O peripheral may have multiple control registers. These control registers are multiple I/O Ports (addresses) in the processor ), writing data to this address is to write data to the Register corresponding to the peripherals, and vice versa, it can also be reading. For example, a serial chip may have multiple registers, one is used to query the chip status, the other is used to set the chip function, and the other is used to read the data received by the chip from the serial line. Finally, another one is used to write data to the chip to send data online to the serial port. The registers of this serial port chip are independent I/O ports from the processor perspective.
I/O ports have read and write problems. Some ports are read-only, some ports are write-only, and some ports can be read or written, the read/write performance is determined by the registers of the peripheral chip, which can be found in the chip data manual. It should be noted that some memory peripherals also have I/O ports to control them. According to the name of the I/O port, an interface for the processor to read data from the outside or output data to the outside is a general term.
---- Interruption is a signal line that can generate high and low levels from the hardware point of view, but it must be understood from the processor point of view. As we have said, from a micro perspective, the work done by the processor is performed in order, and its processing of the program can only be the execution of one instruction and one instruction. If you need to access the peripheral chip, and it is possible that after the processor sends a read or write command, the peripherals are usually much slower than the processor, therefore, it takes some time for the peripheral chip to prepare the required data. In this case, if the processor waits until the output data of the peripheral chip executes Subsequent commands, it will take precious time and the time can be used for other work. Don't forget, from a macro perspective, the processor is often multitasking, and the task is the scheduling unit provided by the operating system. When a task is blocked by waiting for data from the peripheral chip, we can switch to another task to improve processing efficiency. This is a problem. When the processor processes another task, what if the data on the peripheral chip is good? Right! It is through the interrupt signal. The high and low levels of Interrupt signals can be used to indicate whether there is an interruption and the processor needs to pay attention to it to handle specific events (for example, events that have been prepared for peripheral data ).
From this point of view, the introduction of interruptions can greatly improve the processing efficiency. In order to use the interrupt on the processor, We need to initialize the interrupt controller of the processor at the beginning, such as installing the necessary interrupt service program or calling it ISR (interrupt service routine). Then, enable the interrupt shielding bit. The following operations must be performed in the interrupted service program:
---- In the development of embedded systems, we need to deal with peripheral chips. When debugging the driver, in addition to fully understanding the data manual of the chip, and in the process of software height, we also need to check whether the expected signal level occurs on the chip. For example, when writing a driver, we need to write an I/O port to operate the peripheral chip. When writing the corresponding I/O port, we know that the chip selection signal of the corresponding chip should be effective. Sometimes, we need to verify whether it happened as expected, which requires an oscilloscope. Generally, an oscilloscope can observe the signal state of two signal lines at the same time. The oscilloscope provides certain functions, such as signal capturing. One of the most important parameters of an oscilloscope is its collection frequency. According to the nycept theorem, if we want to use an oscilloscope to view signals with a frequency of M Hz, therefore, the sampling frequency must be at least two times, namely, M Hz. Someone may ask: why not use a multimeter? Because the acquisition frequency of the multimeter is very low, the rapid signal changes cannot be collected.
---- The logical analyzer is simply an oscilloscope with many signal channels. Through the logic analyzer, we can see the data on the address bus and the data bus. The logical analyzer provides certain programming capabilities for programming when to start to collect data on the bus. Reproduced in: http://blog.csdn.net/ce123/article/details/6970131
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