2.3.1 Linear equalizer (Linear equalizer) The target of the receive-side equalizer is consistent with the send equalizer. For low-speed (<5gbps) SerDes, typically in a continuous time domain, a linear equalizer is implemented such as a spike amplifier (peaking amplifier), and the gain of the equalizer over the high frequency component is greater than the gain of the low frequency component. Figure 2.8 is the frequency domain characteristic of a linear equalizer. Typically, the factory encapsulates several levels of equalization characteristics, which can be dynamically set to accommodate different channel characteristics, such as High/med/low.
Figure 2.8 Frequency Response of A peaking amplifier based Rx equalizer 2.3.2 DfE equalizer (decision Feedback equalizer)
For high-speed (>5gbps) SerDes, the linear equalizer alone is no longer applicable because signal jitter (such as ISI-related deterministic jitter) can exceed or approach a symbol interval (UI, Unit Interval). The linear equalizer amplifies the noise and signal, and does not improve Snr or BER. For high-speed serdes, a nonlinear equalizer called the DfE (decision Feedback equalizer) is used. DfE predicts the sampling threshold for the current bit by tracking data from past multiple UIs (history bits). The DfE only amplifies the signal and does not amplify the noise, which effectively improves the SNR.
Figure 2.9 illustrates a typical 5-order DfE. The received serial data is determined by the comparator (slicer) to 0 or 1, then the data stream is a filter to predict inter-code interference (ISI), and then subtract the inter-code interference (ISI) from the original input signal, thus to a clean signal. To allow the circuit of the DfE equalizer to operate within the circuit's linear range, the serial signal is first automatically controlled by the VGA to enter the DfE signal amplitude.
To understand how the DfE works, first look at the impulse response of a 10Gbps backplane, which is a test-based model given by MATLAB with typical characteristics.
In Figure 2.10, a horizontal lattice represents the time of a UI. As can be seen, a UI (0.1nS = 1/10ghz) pulse signal, through the backplane, leaked into the front and back of several adjacent UI, thereby interfering with the data of other UIs. The disturbance behind the sampling point is called post-cursor interference, which is called pre-cursor interference in front of the sampling point. The first coefficient H1 of the DfE (in this case 0.175) corrects the first post-cursor, and the second factor H2 (0.075 in this example) corrects the second post-cursor. The more orders of DfE, the more post-cursor can be corrected.
Using the above backplane to transmit a 11011 of the stream, due to the leakage of post-cursor and pre-cursor, if not balanced, will cause ' 0 ' is not recognized, see Figure 2.11. Assuming there is a 2-step DfE, then the magnitude of the ' 0 ' bit should be subtracted from the first ' 1 ' bit of H2, the second ' 1 ' bit of h1, get 0.35-0.075-0.175 = 0.1, enough to be recognized as 0.
As can be seen, the DfE calculates the post-cursor interference of the history bits, subtracting the interference in the current bit, thus obtaining a clean signal. Since DfE can only correct the Post-cursor ISI, the DfE is typically preceded by Le. As long as the coefficients of the DfE are close to that of the channels (channel), the desired results can be reached. But the channel is a time-varying medium, such as the slow change of the temperature and voltage process and other factors will change the characteristics of channel channels. So the coefficients of DfE need an adaptive algorithm that automatically wins and follows the change of the channel. The DfE coefficient adaptive algorithm is very academic, each vendor's algorithm is confidential and not disclosed. For NRZ code, the typical algorithm criterion is based on the Sign-error-driven algorithm. The Sign-error is the error of the amplitude and expected value of the equilibrium signal, the algorithm takes the Sign-error mean variance as the optimization goal, successive optimization h1/h2/h3 ... Since the sign-error and sampling positions are coupled together, it is also possible to predict the DfE coefficients for the target by Sign-error and the eye width of two criteria. Therefore, the serdes with the DfE structure usually comes with an embedded eye-graph test circuit, as shown in Figure 2.9. The eye graph test circuit can translate the amplitude of the signal vertically, translate the sampling position horizontally, calculate the BER ber at each translation position, and get the "eye graph" of each offset position and bit error rate, see Figure 2.12.
Figure 2.12 SerDes Embedded Eye-diagram Test Function