Understanding of settling time, holding time, establishing allowances, maintaining allowances

Analysis Description: D2: Destination register; D1: source register; Edge2: Next clock rising edge; Edge1: current clock rising edge; EDGE0: The previous clock along the rising edge of the current clock;

Settling time: Trigger D2(where the data is going to reach the destination) at the clock rising edge Edge1(with Edge1 being the current clock rising edge) the input data data1(Data1 is edge0 when D1 calls the data of D1, Or the output of a edge0 moment D1. EDGE0 is the previous rising edge of the Edge1 T_setup requires data1 data to be stable (why is this required?). ). It is clear that settling time is a time requirement for D2 input data, or data1 to arrive at D2 some time before edge1.

1. Why is it required to establish time?

to make the data correct of the latching requires that the data be stable, if the implementation circuit of the trigger is known. If the time of Edge1-t_setup to Edge1 is likely to change, it will cause not knowing whether the latch is 1 or 0, which is one of the metastable conditions described. This makes it impossible to reliably transmit data. So it takes time to set up.

2, the Data data1 ( from the trigger D1, that is, the data source ) to transmit to the D2 input, this data data1 arrived D2 time T12 how to calculate it?

A very small time after the edge0 came T1(can be considered as the propagation delay of the trigger), starting from D1, through the combination of logic delay T2, reached D2 ( destination of the data ). The answer already knows t12= T1 + T2. ( be sure to note that the current moment is edge1, the analysis of T12 is edge0 as the reference clock.) Why would you do that? Look at 3 little dots. At this point the clock arrives at the D2,D1 the difference is not considered, namely the clock jitter. There are T2 generally give the maximum delay, the minimum delay is T2max, t2min. What is the specific use of the view??? Wait, say ....

3, at the current moment Edge1 D2 data1 settling time, that data1 when the data from the D1 output it?

again, the settling time is the data time requirement for analyzing the D2 input. This is the moment when the data at the EDGE1,D2 input is emitted by D1 ( assuming that in the synchronization system, why do you make this assumption?). )? It must be at some edge, or ... edge2,edge1, or Edge0,edge ( -1),.........。 What if it's only started when the edge1? Think about .... It is impossible to meet the settling time! Push to see: Suppose Edge1 can meet settling time. What is the requirement? Calling CLK's edge1 to D2 is much slower than D1 here: T12 + t_setup. This allows all edge to reach the destination register at least slower than the T (t combination logic delay ) +t_setup. I don't know how to achieve this kind of synchronization system. If it is in Edge2,edge3, ...    Time only issued data1, to meet the establishment time is not more impossible to achieve? What happens if the data is transferred at EDGE0? It is obvious that the data data1 has a CLK time to transmit, because in advance a CLK D1 will data1 out, as long as the data1 can reach Edge1-t_setup at the D2 of the time before the input can meet the settling time. What are the advantages of this analysis? I am not too professional, anyway, this analysis feels very right. This is also the point at which the current Time series analysis tool defaults data1 data from D1 . This is Requirements ofdata transmission timing, actual hardware circuitry but whatever it is, these are just the requirements we want. It's only as long as the data is stable when it asks for stability. The same is true for the multiple cycles that follow. What happens if you start the output at Edge (-1)? Because the D2 requires data1 stable time or constant, namely: Edge1-t_setup. So Data1 has 2 * CLK time to transmit. It is clear that this will be more satisfying before the edge1-t_setup of the requirements of stability. This is the System tool (such as Quartus's Timequestused in the specified multi-cycle. such as Edge ( -2), Edge (-3), ... is a multi-cycle analysis.

4. How does the data1 data go?

The assumption is not multi-cycle ( because I have not been able to analyze the multi-cycle analysis ) DATA1 data transmission at all times is very easy to mistake. because the output of D2 at edge1 time is not data1, then what is the data of D2 output at this time? must be the output of Edge ( -1) D1 . At what point does the data1 output? The EDGE2+T1 (T1 can be thought of as the propagation delay of the trigger) is output from the D2. This will explain why the data passes through a layer of triggers, and it is necessary to delay one more clock. How can the data1 be correctly output by D2? Or in Edge0, how can data1 correctly output from D1? This is the requirement to meet the hold time. This means that only the hold time data is met to be correctly sent by D. Just want to discuss in the hold time.

5, how to calculate data1 meet D2 hold time?

The time that data arrives D2 is earlier than D2 require data to stabilize, say data1 meet D2 hold time. Assuming that a CLK is in advance, then t_q (this is not a good description,,, in a clock cycle in addition to the time remaining in the transmission time ) = clk-t12, at this time can be determined T12 in the T2 is the smallest or the largest? In order to analyze the insurance t2 = T2max, so the data1 arrival time will be delayed, so it is more likely to not meet the D2 to data1 settling time. As long as T_q = clk-t2max-t1 > T_setup (t_setup is also a time period ), it is said that Data1 is satisfied by D1 output to the settling time of the D2 input. T_q > T_setup are relative time periods. is not the time on the timeline. It would be nice if I could mark it on the timeline. I'm not going to sign it. I write: |t_q| (data1 timeon the timeline output from D1 to D2 ) = Edge0-t2max-t1, |t_setup| (D2 requires data1 to stabilize the time axis) = Edge1-t_setup. The standard for settling time at this time is |t_q| on the left side of the timeline, |t_setup| on the right side of the timeline |t_q| < |t_setup|. this time (edge1) do not think of data1 in the D2 output, because this time data1 as long as waiting, not to the output .

6. the margin t_setup_slack of settling time?

Here it is clear that Data1 reached the D2 of a CLK within the remaining time to reduce the D2 required to establish the time period is the balance of settling time: T_setup_slack = T_q ( in a clock cycle in addition to the time remaining in the transmission time )-T_setup. That is, the settling time margin is greater than 0, can meet the data1 from the D1 transmission to D2, a clock cycle to meet the settling time.

7. How do you embody this relationship in Verilog?

In Verilog to generate a trigger must have this sentence always @ (Posedge CLK or Negedge rst_n), there is not necessarily a trigger to produce this sentence. Take a look at the following code:

 always @ (posedgeornegedge rst_n)    begin    if(!  Rst_n)        0;     Else if 1 )        1;     Else  0;          End

byte_flag is also clk_200m synchronous and has a maximum of one clock high. Can you detect byte_flag = = 1 in this code? The tx_start_flag here is a trigger. Byte_flag is the output of a trigger ( data source ). At clk_200m edge0 time, Byte_flag output data 1, this time will be judged by the above execution Tx_start_flag <= ( non-blocking ) 1; at this point the analysis is the settling time, and at this time the Tx_start_flag output is still 0. Why is the output still 0 at this time? Not already running the Tx_start_flag <= (non-blocking) 1; , huh? My understanding is that the output of Tx_start_flag at edge0 time is the value that edge (-1) satisfies the settling time. Still this sentence, the establishment time analysis is the input, the execution of this sentence Tx_start_flag <= (non-blocking) 1; Also just give the input of the Tx_start_flag trigger in Edge0, execute the tx_start_flag <= ( non-blocking ) 1; The output of the Tx_start_flag (trigger) at EDGE0 time is not affected. At edge1 time, Byte_flag output data 0, the same as the selector will perform Tx_start_flag <= ( non-blocking ) 0; At this point the Tx_start_flag output is 1, which is the wait for the settling time of the EDGE0 to be output ( to meet the hold time, of course ). Summing up the behavior of this always @ (Posedge CLK or Negedge rst_n) 1) gives the output that satisfies the hold time, which is the input of the previous edge that satisfies the settling time, and first updates the output. 2) After the judgment execution statement, the trigger input satisfies the settling time. (input, the output is concurrency, there is no order, here's 1) is done first). It is clear that the Byte_flag has a high pulse that will cause the tx_start_flag to produce a high pulse.

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Hold time: At the time of the CLK Edge1 (at the Current time ) the D2 (t_hold), the input data should be stable. As long as the data at the input end of the t_hold is stable, the input data can be stably output.

1. What is the output time?

After the Edge1 arrives at D2 ( without considering the difference between the clock arrival d1,d2 or the clock offset ), assume that the input data is stable at this time ( because only want to know the time of the output, that is, assuming that the settling time is met ), The time required for data output can be called the transmission delay of the trigger T1 that is the required hold time. If you really want to hold T1 by what part: This depends on the trigger to form the gate circuit, the more fine point to see the process of making the CMOS of the gate circuit ( do not know understand, anyway, the time is short 0. Several ns). T_hold > T1. You can estimate that the hold time should be very short.

2, what will lead to this period of time the input data instability?

The timing can be controlled in Edge1 ( why Edge1, not ... edge (2), Edge (0), Edge ( -1), ... At a time from the output data1 of D1, after a period of T12 ( data from D1 to D2 time ) to reach D2, if the time of arrival destroyed Edge1 to output data date0 (edge0 time to reach D2 data ). If this condition is met the requirement is T12 < T_hold. If edge2 time D1 output data data2 to destroy Edge1 time D2 data data1 output, what are the requirements? D1, the data that is lost at edge2 time runs faster than the data output at the time of Edge1. This is unrealistic, because DATA1,DATA2 is walking the same circuit. And EDGE0 is the data to be edge1 output. Summary: The only reason to undermine stability is T12 < T_hold.

3, maintain the margin?

First of all to meet the retention time is stable, namely: T12 > T_hold, only to maintain the margin. The retention margin is: t12-t_hold. But one of the questions is whether T2 takes Max or Min, in order for the data to arrive at the fastest speed, that is, t2 = T2max. That is T12 = T2min + t1-t_hold.

4, data1 destroy DATA0?

Edge1 the time to meet the Hold is data0 (D2 edge1 output Data ), Data1 is D1 at edge1 time output to D2 in order to meet Edge2 D2 the settling time of the output. If the data1 arrives D2 too fast, it is possible to destroy D2 DATA0 data in the Edge1 output. This is a small possibility, but it still exists. such as D1_t1 = 0.06ns, t2 = 0.06ns ( no combination logic ), D2_t_hold = 0.2ns, regardless of clock offset. T12 = 0.06 + 0.06 = 0.12ns < D2_t_hold = 0.2ns. This is not related to the CLK cycle.

Summary: The transfer of data to be clarified. So you can understand the timing.

Have a day to write it well. It seems that the matter is serious or can be done!! This process, the result .... 2015.4.24 Cornhill

Understanding of settling time, holding time, establishing allowances, maintaining allowances