Understanding of the W5500 interrupt register

The W5500 interrupt section is not clear enough in the W5500 Chinese Manual V1.0. This article is based on the Chinese and English manuals and their own understanding, to sort out the understanding of the interrupt section. Please correct me if there is any incorrect one.

 

I. Pin INTn is the Interrupt output (Interrupt output)

Low: the W5500 interrupt takes effect;

High level: no interruption or in waiting for the interruption to take effect

 

II. Interrupt registers

2.1 IR (connection interrupt register) [R/W] [0x0015] [0x00]

This register indicates network connection error or wake-up interruption.

If a bit is 1 and the bit interrupt is not blocked, the interrupt can be triggered. The INTn pin will be lowered. After the interrupt processing is completed, the host can write '1' to clear the bit interrupt. when the IR value is '0 × 00', the INTn pin is increased.

2.2 IMR (connection interruption shielding register) [R/W] [0x0016] [0x00]

The interrupt shielding register (IMR) is used to block IR interruptions. If you write '1', the interrupt is enabled. If you write '0', the interrupt is disabled.

Each interrupt shielding bit corresponds to one of the interrupt registers (IR. if IMR writes 0, the INTn pin will not be dropped even if the corresponding bit in IR is 1.

2.3 SIR (Socket interrupt register) [R/W] [0x0017] [0x00]

SIR indicates which Socket is interrupted.

If a Socket is interrupted, the corresponding bit of the register will be set to 1 until the host sets '1' to clear. If Sn_IR is not equal to '0 × 00', it will interrupt and the INTn pin will be dropped.

2.4 SIMR (Socket interrupt shielding register) [R/W] [0x0018] [0x00]

The SIMR register is used to block the SIR interrupt. If a certain value is '1', the interrupt is enabled. If the value is '0', the interrupt is disabled.

Each interrupt shielding bit corresponds to one of the interrupt registers (SIR. if a SIMR writes 0, the INTn pin will not be dropped even if the corresponding bit in the IR is '1.

 

2.5 Sn_IR (Socket n interrupt register) [R] [0x0002] [0x00]

The Sn_IR register is used to provide Socket n interrupt type information, such as Establishment, Termination, processing data, and Timeout ). When an interruption is triggered, that is, when the corresponding bits of Sn_IMR are '1', the corresponding bits of Sn_IR will also become '1 '.

If you want to clear the Sn_IR bit, the host should set this location to '1'

[R] here, rather than [R/W], indicates that the host cannot write '1' to interrupt the W5500. The host can only set '1' to clear a certain interrupt.

2.6 Sn_IMR (Socket n interrupt shielding register) [R/W] [0x002C] [0xFF]

Sn_IMR is responsible for shielding Socket n interruptions. If you write '1', the interrupt is enabled. If you write '0', the screen is closed.

Each bit corresponds to the corresponding bit of the Sn_IR register. When the Socket n is triggered and the corresponding bits of Sn_IMR are '1', the corresponding bits of Sn_IR are changed to '1 '. If the corresponding bits of Sn_IMR and Sn_IR are '1' and the SIR register is '1', the INTn pin will be lowered and the host will be interrupted.

2.7 INTLEVEL (low-level interrupt timer register) [R/W] [0x0013-0x0014] [0x0000]

This register is used to set the wait time for the interrupt to take effect (IAWT ). When the next interrupt is triggered, the interrupt pin will lower the interrupt pin (INTn) after the INTLEVEL time ).

Assume that two interruptions occur in a certain period of time, Socket 0 and scoket1.

A. When the timeout interrupt of Socket 0 is triggered, SIR [0] & S0_IR [3] is set to '1', indicating that A timeout interrupt occurs for 0th sockets. Then the INTn pin is pulled down, notifying the host that it was interrupted.

B. when the connection interruption of Socket 1 is triggered before the previous interrupt is not completed, the INTn pin is still low, and the S1_IR [0] & SIR [1] bit is set to '1 '.

C. if the host is interrupted and the S0_IR [3] bit and SIR [0] are cleared, the S1_IR [0] & SIR [1] is still '1 ', the INTn pin will still be pulled up.

D. Even if the S1_IR [0] & SIR [1] bit is set to '1', INTn cannot be lowered during INTLEVEL. INTn can be lowered only after INTLEVEL time.

III. Interrupt design procedure

Through the above introduction, we can see the following relationship between several registers:

A: Three interrupt register IR, SIR, Sn_IR, which correspond to the three interrupt shield registers IMR, SIMR, and Sn_IMR (which can also be considered as the interrupt enable register ). Only when the enable bit is interrupted and the bit is '1' can interrupt and reduce INTn.

B: After an interrupt processing is completed, INTn is increased after the corresponding status bit is cleared. If another interrupt status register is '1', INTn is lowered after a certain period of time. This time is set by the INTLEVEL register. Only one event can be handled for one host interruption.

C: The registers related to the network connection status are not directly related to SIR and Sn_IR. While SIR and Sn_IR appear at the same time, SIR points out that the nth Socket has an interruption event, and Sn_IR points out what type of interruption events happened to Socket n, such as receiving data timeout.

Therefore, if the host adopts the interrupt mode and INTn is detected to be pulled down, you can use the interrupt service function to determine whether the IR is interrupted, instead of reading the SIR status, find the Socket n that triggers the interruption, and then read the corresponding Sn_IR for processing. After each processing, the corresponding register of the host needs to be cleared.

By William

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Understanding of the W5500 interrupt register