Understanding of the simulation GLBL.V file

Simulation, UniSIM, simprim-how do I use the ' glbl.v ' module in a Verilog Simulation? Description

How does I use the ' glbl.v ' module in a Verilog simulation?

Solution

The "GLBL.V" module connects the global Set/reset and global Tristate signals to the design. In order to properly reset the design in a Verilog simulation, the "GLBL.V" module must is compiled and loaded along with The design. The "GLBL.V" module is located at "$XILINX/verilog/src/glbl.v".

Using 6.1i design Tools and later

In the 6.1i design tools, the "GLBL.V" module is modified to automatically pulse GSR (FPGA Global set/reset) and Prld (CP LD Global Set/reset) for the first of the simulation. Code was also added to automatically pulse Global Tristate (GTS) and the default pulse is 0 ns.

For exact commands on what compile and load the "GLBL.V" in Modelsim, see the following solutions:

(Xilinx Answer 1078)-Behavioral Simulation

(Xilinx Answer 10177)-Post-par Timing Simulation

For additional information, reference the Synthesis and Simulation Design Guide:

Http://toolbox.xilinx.com/docsan/xilinx6/books/docs/sim/sim.pdf
In Chapter 6, verifying Your Design, there are a section on "Understanding the Global Reset and Tristate for Simulation."

Using 5.1i/5.2i design tools and earlier versions

Prior to the 6.1i release, the "GLBL.V" module does not automatically pulse the GSR or Prld signal. It is therefore necessary to drive GSR or Prld and/or GTS from the Testbench. This is the code, needs to being added to the testbench:

Reg GSR;

Assign Glbl. GSR = GSR;

Reg GTS;

Assign Glbl. GTS = GTS;

Initial begin

GSR = 1;

#100 GSR = 0;

End

NOTE 1:for CPLD Designs, replace GSR with Prld in above the code.

NOTE 2:gts can also be driven, but it's generally not necessary unless you are doing a board-level simulation.

For exact commands on what compile and load the "GLBL.V" in Modelsim, see the following solutions:

(Xilinx Answer 1078)-Behavioral Simulation

(Xilinx Answer 10177)-Post-par Timing Simulation

For additional information, reference the Synthesis and Simulation Design Guide:

Http://toolbox.xilinx.com/docsan/xilinx6/books/docs/sim/sim.pdf
In Chapter 6, verifying Your Design, there are a section on "Understanding the Global Reset and Tristate for Simulation."

Xilinx FPGAs has a register (flip-flops and latches) Set/reset circuitry that pulses at the end of the configuration mode. This pulse was automatic and does not need to be programmed. All the flip-flops and latches receive this pulse through a dedicated global GSR (global Set-reset) net. The registers either set or reset, depending on how the registers is defined.

For some device families, it's important to address the built-in reset circuitry behavior in your designs starting with T He first simulation to ensure, the simulations agree at the three primary points.

For the Virtex and spartan-ii device families, Xilinx recommends using the manual reset instead of the dedicated GSR CI Rcuitry. This was because the implementation tools use the high-speed backbone routing for Reset signals, thus making them faster th An the dedicated global routing which transports the GSR signal. However, for the XC4000 and Spartan device families, GSR is the better method of propagating the global reset signal.

For the XC4000 and Spartan device families, if you don't simulate GSR behavior prior to synthesis and place and route, Your RTL and possibly post-synthesis simulations might not initialize to the same state as your post-route timing Simulat Ion. As a result, the various design descriptions would not be functionally equivalent and your simulation results would not MATC H. Some synthesis tools can identify, from the behavioral description, the GSR net, and would place the "STARTUP module on T" He net to direct the implementation tools to use the global network. However, other synthesis tools interpret behavioral descriptions literally, and would introduce additional logic into your Design to implement a function. Without specific instructions to use device global networks, the XILINX implementation tools would use general purpose Logi C and Interconnect resources to redundantly build functions already provided by the silicon.

If GSR behavior is not described, the chip would initialize during configuration, and the Post-route netlist would include T The He net that must is driven during simulation. This section includes the methodology to describe this behavior, as well as the GTS behavior for output buffers.

In addition to the set/reset pulse, all output buffers is set to a high impedance state during configuration mode with th E dedicated global output tristate enable (GTS) net.

The GSR net requires special handling during synthesis, simulation, and implementation to prevent them from being assigned To normally routed nets, which uses valuable routing resources and degrades design performance. The GSR net receives a reset-on-configuration pulse from the initialization controller, as shown in the following figure.

Figure 6-2 Built-in FPGA initialization circuitry

This pulse occurs during the configuration mode of the FPGA. However, for ease of simulation, it's usually inserted at time zero of the test bench, before logical simulation is Initi Ated. The pulse width is device-dependent and can vary widely, depending on process voltage and temperature changes. The pulse is guaranteed to being long enough to overcome all net delays on the reset Special-purpose net. The parameter for the pulse width are tpor, as described in the Programmable Logic Data book.

The Tristate-on-configuration circuit shown in the "built-in FPGA initialization circuitry" also occurs during the Configu Ration mode of the FPGA. Just As for the reset-on-configuration simulation, it's usually inserted at time zero of the test bench before logical Si Mulation is initiated. The pulse drives all outputs to the tristate condition they is in during the configuration of the FPGA. All general-purpose outputs is affected whether they is regular, tristate, or bi-directional outputs during normal opera tion. This ensures, the outputs do not erroneously drive and other devices as the FPGA are being configured. The pulse width is device-dependent and can vary widely with process and temperature changes. The pulse is guaranteed to being long enough to overcome all net delays on the GTS net. The generating circuitry is separate from the Reset-on-configuration circuit. The pulse width parameter is Tpor, as described in the Programmable Logic Data book. Simulation models Use this PulsE width parameter for determining HDL simulation for global reset and tristate circuitry.

If a global set/reset is desired for behavioral simulation, it must being included in the behavioral code. Any described register in the code must has a common signal that would asynchronously set or reset the register depending On the desired result. Similarly, if a global tristate-state is desired for simulation, it should being described in the code as well.

Reference

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Understanding of the simulation GLBL.V file