Understanding successive approximation register ADC: Architecture comparison with other types of ADC

Abstract: The successive approximation register type (SAR) ADC occupies most of the medium to high resolution ADC market. The sar adc has a maximum sampling rate of 5 MSPs and a resolution of 8 to 18 bits. The SAR architecture allows high-performance, low-power ADC to use small-size packages and is suitable for systems with strict size requirements.

This article describes how sar adc works and converts input signals using a binary search algorithm. This article also provides the core architecture of sar adc, that is, Capacitive DAC and high-speed comparator. Finally, we compare the SAR architecture with the pipeline, the Flash speed model, and the Σ-△adc.

Introduction

The SAR analog digital converter (ADC) is a common structure for medium to high resolution applications with a sampling rate lower than 5 MSPs (Millions of samples per second. Generally, the resolution of sar adc is 8 to 16 bits, featuring low power consumption and small size. These features enable this type of ADC for a wide range of applications, such as portable/battery power meters, Pen Input quantifiers, industrial controls, and data/signal collection.

As the name implies, sar adc is essentially a binary search algorithm. Therefore, when the internal circuit runs at several MHz, the ADC sampling rate is only a fraction of the value due to the successive approximation algorithm.

Architecture of SAR ADC

Despite the wide variety of methods for implementing sar adc, the basic structure of sar adc is very simple (see figure 1 ). Analog Input voltage (V_{In) is maintained by the sampling/holding circuit. To implement the binary search algorithm, the N-bit register is first set to the intermediate scale (that is, 100... 00, and MSB is set to 1 ). In this way, the DAC output (VDAC) is set to VRef/2, VRef is the reference voltage provided to the ADC. Then, compare and Judge VWhether in is smaller than or greater than VDAC. If VIn is greater than VDAC, the MSB of the N-bit register of the comparator output logic is 1 or 1. Conversely, if vIn less than VDAC, the comparator output logic is low, and the MSB of the N-bit register is 0. Then, the SAR control logic is moved to the next position, and the bit is set to a high level for the next comparison. This process continues until LSB. After the above operation, the conversion is completed, and the N-bit conversion result is stored in the register.}

Figure 1. Simple N-bit sar adc Architecture

Figure 2 provides a 4-bit conversion example. The Y axis (and the rough line in the figure) represents the output voltage of the DAC. In this example, the first comparison indicates_{In <vDAC. Therefore, the value of bits 3 is 0. The DAC is set to 0100.2, and perform the second comparison. Because VIn>
VDAC, bit 2 is kept as 1. DAC to 01102. Perform the third comparison. Based on the comparison results, the bit 1 is set to 0, and the DAC is set to 0101 again.2. Execute the last comparison. FinallyIn> VDAC, bit 0 is determined as 1.}

Figure 2. How SAR works (taking 4-bit ADC as an example)

Note: For a 4-bit ADC, four comparison cycles are required. Generally, the N-bit sar adc requires n comparison cycles. The next conversion is not allowed until the previous conversion is completed. It can be seen that this type of ADC can effectively reduce power consumption and space. Of course, it is precisely for this reason that the resolution is between 14-16 bits and the speed is higher than several MSPs (Millions of samples per second) gradually approaching ADC is rare. Some Sar-based micro-ADCs have been pushed to the market. Max1115/max1116 and max1117/max1118 8-bit ADC and interchangeable products with higher resolution max1086 and max1286
(10 bits and 12 bits respectively) in a tiny sot23 package with a size of only 3mm x 3mm. 12-bit max11102 is packaged in 3mm x 3mm tdfn or 3mm x 5mm µmax.

Another notable feature of sar adc is that power consumption changes with the sampling rate. This is different from the flash ADC or pipeline ADC, which has fixed power consumption at different sampling rates. This variable power consumption feature is very advantageous for low-power applications or applications that do not require continuous data collection (for example, PDA digital converter ).

In-depth analysis of SAR

Two important components of the sar adc are the comparator and DAC. We can see later that the sampling/Holding Circuit in Figure 1 can be embedded into the DAC, instead of being an independent circuit.

Sar adc speed is limited:

· The DAC establishment time must be stable within the resolution of the entire converter (for example :? LSB)

· Comparator, which must be able to distinguish the tiny differences between VIN and vdac within the specified time

· Logical overhead

DAC

The maximum creation time of a DAC is usually determined by the creation time of its MSB. The reason is simple. The change of MSB represents the maximum offset of the DAC output. In addition, the linearity of the ADC is also limited by the DAC linear indicator. Therefore, due to the limited inherent matching degree of components, SAR ADCs with resolutions higher than 12 bits often need to be adjusted or calibrated to improve their linear indicators. Although this depends on the processing process and design to some extent, in the actual DAC design, the matching degree of components limits the linear indicator to about 12 bits.

Many SAR ADCs use capacitive DAC with inherent sampling/holding capabilities. Capacitive DAC generates analog output voltage based on the principle of charge redistribution. Because this type of DAC is often used in sar adc, we 'd better discuss their working principles.

Capacitive DAC includes an array consisting of n capacitors in binary weighted order and an "empty lsb" capacitor. Figure 3 shows an example of a 16-bit capacitive DAC connected to a comparator. In the sampling phase, the Public end of the array (all the public points connected by capacitor, see Figure 3) is grounded, and all free ends are connected to the input signal (analog input or V_{In ). After sampling, the public end is disconnected from the ground, and the free end and VThe in is disconnected, and the amount of charge proportional to the input voltage is effectively obtained on the capacitor array. Then, ground the free ends of all capacitors to drive the public end to a negative pressure-VIn.}

Figure 3. 16-bit capacitive DAC example

As the first step of the binary search algorithm, the bottom of the MSB capacitor is disconnected from the ground and connected to V_{Ref to drive the voltage at the public end to move forward vRef.}

Therefore, V_{Common =-VIn + records × VRef}

If V_{Common <0 (that is, VIn> memory × VRef), the comparator output is logical 1. If VIn <
Limit × VRef. The output of the comparator is logical 0.}

If the comparator output is logical 1, the bottom of the MSB capacitor remains connected to V_{Ref. Otherwise, the bottom of the MSB capacitor is connected to the ground.}

Next, connect the bottom of the next small capacitor to V_{Ref.The common voltage is compared with the ground potential.}

Continue the above process until the values of all BITs are determined.

In short, V<sub>Common =-VIn + BN-1 X vRef/2
+ BN-2 X vRef/4 + BN-1 X vRef/8 +... + B0 × VRef/2^{N-1 (B _ is the comparator output/ADC output bit ).}</sub>

DAC Calibration

For an ideal DAC, each capacitor that corresponds to the data bit should be twice as accurate as the next small capacitor. In a high-resolution ADC (such as a 16-bit ADC), this results in an excessively wide Numerical range and cannot be achieved in an economical and feasible size. A 16-bit sar adc (such as max195) is actually composed of two capacitance columns. The capacitance coupling is used to reduce the equivalent capacity of the LSB array. The capacitance in the MSB array is fine-tuned to reduce the error. Minor changes to the LSB capacitor will produce significant errors in the 16-bit conversion results. Unfortunately, tuning alone cannot reach 16-bit accuracy, or compensate for performance metrics changes caused by changes in temperature, power supply voltage, or other parameters. For the above reason, max195 has configured a calibration DAC for each MSB capacitor. These DAC are coupled to the master DAC output by capacitance, and the output of the master DAC is adjusted according to their digital input.

On-time correction, you must first determine the correction code used to compensate each MSB capacitor error and store the code. After that, when the data bit corresponding to the primary DAC is high, the stored code is provided to the appropriate calibration DAC to compensate the error of the relevant capacitor. The user initiates the calibration process or performs automatic calibration upon power-on. To reduce the noise effect, each calibration process is performed many times (max195 lasts about 14,000 clock cycles) and the results are averaged. When the supply voltage is stable, it is best to perform a calibration. High-resolution ADC should be re-calibrated after a significant change in any parameter, such as power supply voltage, temperature, reference voltage, or clock, because these parameters have an impact on the DC offset. If only linear indicators are taken into account, these parameters can be greatly changed. Because calibration data is stored in numbers, sufficient accuracy is maintained without frequent conversions.

Comparator

The comparator must have sufficient speed and accuracy. Although the offset voltage of the comparator does not affect the overall linearity, it will bring a deviation to the system transmission characteristic curve, the offset elimination technology is introduced to reduce the offset voltage of the comparator. However, noise must also be considered. The equivalent input noise of the comparator must be within 1 LSB. The comparator must be able to tell the voltage within the accuracy of the entire system, that is, the comparator must ensure the accuracy comparable to that of the system.

Comparison between sar adc and other ADC Structures

Compared with the pipeline ADC

The pipeline ADC adopts a parallel structure. Each level in the parallel structure performs one or several successive Sampling operations at the same time. This inherent parallel structure increases data throughput at the cost of power consumption and latency. Latency is defined as the time difference between the time when the ADC samples analog input and the time when the output end gets quantified data. For example, a 5-level pipeline ADC has at least five clock cycle latencies, while SAR only has one clock cycle delay. It should be noted that the definition of latency is only relative to the ADC throughput, not the internal clock of SAR, which is many times the throughput. The pipeline ADC requires frequent digital error calibration to reduce the ratio of each level of flash ADC on the pipeline
(That is, comparator) accuracy requirements. The accuracy of the sar adc comparator is equivalent to that of the overall system. Pipeline ADC generally requires more Silicon Wafer area than SAR of the same level. Like SAR, a pipeline ADC with a precision higher than 12 bits usually requires some form of fine-tuning or calibration.

Compared with the flash ADC

The flash ADC consists of a large number of comparator, each of which includes a broadband, low-gain pre-amplifier, and latches. The pre-amplifier must be used only to provide gain without high linearity and precision, which means that only the threshold value of the comparator must have high accuracy. Therefore, the flash ADC is currently the fastest-performing architecture.

Generally, the speed of the flash ADC and the low power consumption and small size characteristics of the sar dac need to be considered in a compromise. Although the extremely high-speed 8-bit flash ADC (along with their folding/interpolation variants) has a sampling rate of up to 1.5gsps (for example, max104, max106, and max108 ), however, it is difficult to find a 10-bit flash ADC, while a 12-bit (and higher) flash ADC is not commercially available. This is because each time the resolution is increased by 1 bit, the number of comparator in the flash ADC will multiply, and the accuracy of the comparator must be twice that of the system. In sar adc, more precise components are required to improve resolution, but the complexity does not increase exponentially. Of course, SAR
The speed of the ADC cannot be compared with that of the flash ADC.

Compared with the Σ-△converter

Traditional oversampling/Σ-△converters are widely used in digital audio applications with a bandwidth limit of around 22 kHz. Recently, some bandwidths from 1 MHz to 2 MHz are available, with a resolution of 12 to 16 bits. This is usually composed of a High-Order Σ-△modulation (for example, level 4 or higher) combined with a multi-bit ADC and multi-bit feedback DAC. The Σ-△converter has an inherent advantage over the sar adc: no special fine-tuning or calibration is required, even if the resolution reaches 16 to 18 bits. Because the sampling rate of this type of ADC is much higher than the valid bandwidth, you do not need to add a fast-scrolling anti-mixing filter at the analog input end. It is processed by the back-end digital filter. The over-sampling feature of the Σ-△converter can also be used to "smooth" any system noise in the input.

The Σ-△converter is used for resolution at a rate. Because a final sample needs to be sampled many times (at least 16 times, usually more ), this requires that the internal analog circuit of the Σ-△modulation work much faster than the final data rate. The Design of Digital extraction filters is also a challenge, and it consumes a considerable area of silicon wafers. In the near future, the bandwidth of the highest-speed, high-resolution Σ-△converter will not be much higher than a few megahertz.

Summary

To sum up, the main advantages of sar adc are low power consumption, high resolution, high accuracy, and small size. Due to these advantages, sar adc is often integrated with other larger functions. The main limitation of the SAR structure is that the sampling rate is low, and each unit (such as DAC and comparator) needs to achieve the same precision as the overall system.