USB 3.0 Transmission Specifications

Universal Serial Bus (USB) since the advent of the 1996, unified PC external interface, and extended to a variety of consumer products, has long become a part of modern life. Published in 2000, the USB 2.0 high-speed specifications, providing 480Mbps transmission rate, has been more than 10 years of history, with the high-resolution audio-visual applications gradually popularized, frequently gbyte level of audio-visual materials, USB 2.0 bandwidth has gradually stretched.

USB Association in 2008, a new generation of USB 3.0 transmission specifications, the USB bandwidth on the push 10 times times 5Gbps and full duplex bidirectional transmission, and a compatible connector design to ensure the compatibility of the device, and increase the supply current from 5V 500mA to 5V 900mA. With the advent of the control chips in the terminal and the main control terminal, Intel and AMD have successively incorporated the USB 3.0 master into the reference design, and plan to launch the native support chipset, and the popularity of USB 3.0 will be finalized. The key to popularity is the final version of the Master interface specification set by Intel: Extensible Host controller Interface (XHCI) 1.0.

　　USB 3.0 system Architecture and main control end design

The physical device of the USB system consists of three kinds: the host side (host), the perimeter (peripheral), and the Hub (hub). The peripheral end (device) is responsible for providing a single or multiple functionality, such as a human-computer interface device (Human Interface device): A keyboard and mouse, an image device: A scanner, a webcam, a storage device: an external hard drive, a USB flash drive, etc. The hub is between the main terminal and the peripheral side, providing the transfer and exchange of information between the upper and lower layers to provide an easy-to-use device to expand connectivity.

The main control terminal is the core operating device in the USB system, and the device control and data transmission are initiated by the main control side. The operation of the main control end is coordinated by hardware and software, and the operation of the main control end must depend on the hardware and software level of the USB host terminal system:

Detection device connection or removal

Manage the control flow of the main control terminal and peripheral devices

Manage the data flow of the main terminal and peripheral devices

Manage and count the operational status of the system

Provides power to USB devices

Start-up and setting of the device end

Scheduling of data transfer

Device-Side power management

USB Bus Management

Figure 1 System block diagram for USB 3.0 system operation

The dashed line in Figure 1 represents the distinction between hardware and software, and the communication of hardware and software follows the XHCI interface specifications. Blocks above the dashed line represent the software portion of the main terminal, including the following four software layers:

Application software: Provides the specific functions provided by the user USB peripheral device through the standard category service provided by class driver;

Class Driver software: performs USB specific category functions on the host PC. such as storage category software, human-computer interface category software, voice category, etc.

USB Driver (USBD): corresponding operating system and XHCD driver software layer, up through the standard USB Driver interface (USBDI) with the operating system or the device class Driver transfer information;

Host controller Driver (XHCD): The software layer communicates with the master controller through the XHCI interface, providing the interface between the hardware and software of the USB Driver and the XHC controller.

The Software layer section, application software and class Driver software, provides the user with the ability to operate peripheral devices, provided by the operating system or device vendor. While the USB driver and host controller driver are closely related to the operation of the controllers, which are currently provided by the manufacturer of USB 3.0 controllers.

Figure 1 below the dotted line section represents a hardware implementation in a USB system, including a master controller hardware and multiple hubs, multiple peripheral devices.

Host controller (XHC) master control: The hardware ASIC of the USB 3.0 main terminal, provides the XHCI interface for the software execution instruction and transmits the information, provides the downstream entity connection port which supports LS/FS/HS and superspeed operation speed. Hardware design must follow two major specifications: XHCI and USB 3.0 specifications.

USB Device Peripheral Device: A USB Hardware device that provides a specific function, or a hub hardware that extends the USB bus.

In combination with the above architecture, the overall design of the master terminal can be divided into two parts of software hardware:

1. XHCI software, including XHC Driver and USB Driver;

2. XHCI hardware, including XHC Controller for the corresponding software, and USB port portion that provides USB connection.

　　XHCI 0.96 vs. 1.0 comparison

XHCI specifications are developed by Intel. August 2008 first release of the 0.9 preliminary version, the first definition of the USB 3.0 host and PC hardware and software interface specifications, the design of the first USB 3.0 as the main application of the object, and retain the future of the more high-frequency wide interface scalability.

In May 2009, Intel released version 0.96, which was also a compatible version of the earlier designed USB 3.0 Host Controller. In May 2010, Intel released its official finalized version 1.0, becoming the final version of the current USB 3.0 Master specification. The XHCI 1.0 version will also become the mainstream specification for future USB 3.0 controllers.

Figure 2 Basic operation of XHCI

XHCI defined in today's PC system, the software accesses PCI Config space, MMIO space, and performs the control and fast data transfer required by the USB 3.0 master. XHCI the ring as the basic data structure for all actions, for a ring-shaped reservoir data structure that contains three species:

Command ring: System software commands the command ring to the host controller hardware (XHC)

Event Ring: The host controller takes the event ring back status and executes the results to the system software

Transfer Ring: Used to move data at both ends of the system memory and endpoint (Endpoint). Transfer Ting consists of groups of Transfer DESCRIPTOR,TD consisting of one or more sets of Transfer Ring blocks (TRB), which are the basic transmission units in the XHCI data structure. The system software transmits the data block through the TRB, including a set of data buffer pointers, and the status and Control unit.

XHCI 1.0 revised more than 20 chapters to clarify the vague or controversial parts of the XHCI specification development process, and included feedback from key developers, and was also considered to be the future support for the original USB 3.0 chipset design specifications finalized. XHCI 1.0 has also added some design to improve overall system efficiency and user experience. Some of the more important improvements are listed below.

　　Fewer software interrupts

Under normal operation, each event TRB at the end of the event ring, triggering a software outage that causes the CPU to enter the service routine processing software interrupt. However, these software interrupts are not all necessary and meaningful, XHCI 1.0 for this phenomenon, in the normal TRB and Isoch Transfer Trb added the block Event Interrupt (BEI) flag, allowing the system to send event TRB without a software interruption. Fewer software outages mean that the CPU will be consumed less time, and the CPU will be less dependent on it, which is equivalent to improving the performance of the transmission.

　　Error handling

USB is an open interface that supports hot swapping, and most of the compatibility issues need to be answered by error handling to reduce user inconvenience. XHCI 1.0 New Soft retry mechanism, when a USB transmission error occurs, the peripheral device side does not know that the main terminal has stopped part of the endpoint, will continue to wait for the main control side of the attempt again. The Soft retry mechanism can give multiple attempts to respond to this condition.

Isoch Transmission for AV applications, XHCI 1.0 also adds a more rigorous error response mechanism because it does not support Cerr's error response.

　　Low-Power mode support

XHCI 1.0 supports save and Restore Operations. For power-saving modes such as sleep, Hibernate, save and Restore operations on a PC system, the USB system saves the cumbersome steps of restarting the internal state when entering and exiting the power saving mode, and quickly enters and exits the state of power saving. Especially for peripheral devices that are not removed, such as built-in video cameras. In addition to support for USB 2.0 Link Power Management (LPM), XHCI 1.0 is also updated with support for USB2 LPM hardware control mechanism.

　　USB 3.0 host-side authentication

The USB association is currently certified to support the XHCI 1.0 Master Controller, where the XHCI CV (Command Verifier) test program will perform XHCI detail specification testing on the master side to ensure that the master controller complies with the XHCI design specification. The Microsoft WLK 1.5 version has announced that the USB 3.0 Master controller on the future system must conform to the XHCI 1.0 specification. This test will also be the basis for future development of the built-in drivers for USB 3.0 master controllers in Windows.

As for the USB association, the authentication of the master side includes three major parts:

　　Electrical characteristics Measurement

Test whether the physical layer and the circuit design of the USB 3.0 device conform to the specifications of the USB 3.0 specification, including the transmitting end and the receiving end. Transmission end test includes 5Gbps signal quality eye diagram, frequency display specification, time-base error specification, etc. The Receive side test contains the bit error rate under multiple sets of specific time base error specifications. Electrical characteristic measurements ensure that all USB 3.0 solid layer designs have basic transmit receive compatibility. At the same time, the USB 2.0 backwards compatible signal must also conform to the USB 2.0 specification.

　　XHCI/USB Command Verifier Test

The command Verifier (CV) test of the main terminal is different from the peripheral device, except the USB CV of the peripheral device, the main control side must also carry on the CV test to the XHCI design part. CV test for the hardware design of the object to be tested, XHCI and USB fine-grained specification verification, to ensure that the hardware of the object to be tested in full compliance with the XHCI and USB specifications, which for XHCI 1.0 of the test items, is also implemented.

　　Compatibility test

USB Association attaches great importance to the compatibility of the host controller, the main control side for USB 3.0 and USB 2.0 peripheral, must undergo a detailed compatibility test to ensure the quality of future market products.

The compatibility test for the master side includes two major projects: the Gold tree test and a large number of USB 3.0 and USB 2.0 peripheral device tests to test the functional integrity and error handling capabilities of the master hardware and software. The Gold tree test consists of more than 10 types of devices with a variety of classes (class) connected to a multi-tier USB 3.0 and USB 2 hub, while qualified master hardware and software must be able to operate all devices simultaneously with the correct plug-and-Take, hibernate, and error handling capabilities. The main test of hardware design is capable of handling extreme multi-device conditions, and software design has a complete support for various types of devices and error handling capabilities. In addition, the association will test the compatibility of the host terminal with a certified USB 3.0/2.0 device with a total of more than 200, across all USB-defined categories.

　　Conclusion

With the introduction of USB 3.0 reference designs and future native support from Intel and AMD, USB 3.0 is established as a mainstream external connection interface. 10 times times the bandwidth, will also take the application to real-time, high-resolution audio and video editing and output into the development, no longer confined to large-capacity storage devices. The number of ports on the motherboard will also be increased from the early 1-2 interfaces to 6-10 interfaces, and the front panel support will be tested, and the analog design capability of the host controller and the bandwidth processing capability of the multi-interface number can be tried.

USB 3.0 Transmission Specifications