USB2.0 High-speed video capture 68013A Register configuration instructions

Source: Internet
Author: User

Any firmware programming can not be separated from the schematic reference, drawing in the use of USB Slave_fifo transmission mode, the specific configuration and drawings corresponding.

USB_IFCLK: Synchronous slave_fifo mode, input frequency range 5m-48m, the signal is configured inside the FPGA as CMOS camera CMOS_PCLK, the output of the sensor pixel clock, as the data acquisition clock and 68013 synchronous clock with FPGA communication.

Assign usb_data = Cmos_data;

FLAGA/FLAGB/FLAGC/FLAGB: The FIFO status information corresponding to the FX2LP output. Before writing FIFO or read FIFO, we need to judge FIFO internal full, empty and so on.

SLCS:FIFO chip selection signal, external logic control, when the SLCs is invalid, data transmission is not allowed.

Sloe:fifo output Enable, external logic control, when the sloe is invalid, the data line does not output valid data.

Slrd:fifo read signal, external logic control, read FIFO control.

Usb_wr:fifo Write signals, external logic controls, synchronous write, when SLWR is active, each IFCLK rising along the data is written, and the FIFO pointer is incremented.

Assign USB_WR = i2c_config_done & Cmos_href & Usb_trigger

USB_WR allows write FIFO operation when CMOS sensor data line synchronization signal and Usb_trigger are all valid.

usb_pa0: External interrupt signal. The interrupt is triggered by a cmos_vsync signal. This signal is the CMOS sensor pixel data field synchronous signal output. Represents the end of each frame of the image input and the start of the next frame of the image input.

usb_fd[0..7]:8 bit data transfer bit. Inside the FPGA, the signal is connected directly to the output of the sensor pixel.

Assign Usb_data = Cmos_data;//cmos_data is the sensor pixel clock output data bit, 8 bits.

FIFOADR0/FIFOADR1: Select Address line for four FIFO endpoints, external logic control. 68013 internally there are four FIFO.

pktend: Packet end signal. Normally, when the external logic writes data like a FIFO, the data is automatically packaged and transmitted when the number of bytes written to the FIFO endpoint equals the package size set by the firmware. However, when the external logic transmits the packet size of the decimal set, only after a certain number of bytes are written, the pktend signal is valid, and the transmission is automatically packaged regardless of how much external logic is written to it. In the firmware, the setting of the pktend is low-efficient, here directly to the high-processing, indicating that each transmission can only fixed packet size transmission.

Second, USB68013 firmware program interpretation

First, a brief introduction to the firmware programming framework provided by the Cypress allows the user to program the firmware simply by adding a small amount of code to the framework that we provide. A hook function is provided inside the framework, and the user adds their own code to the hook function to complete the programming.

When the firmware resets the power on, it initializes some global variables, then calls the initialization hook function td_init (), interrupts, waits for device re-enumeration to complete, and finally enters the while (1) Loop statement to perform the task scheduling. Here is not specifically the reference source program, the framework of the source files and header files are as follows.

Ezusb. Lib

EZUSB Library file


Ezusb header File


FX2 Register header file


predefined, macro, and function declarations


Firmware Framework source File


A list of USB descriptors that users can modify


Break Jump function Target file


Synchronization delay, defines the program short delay function Syncdelay


C51 some data types and function definitions


External interrupt Processing file


User hook function file, modifiable, user code

In addition, the functions we need to understand include:

void Td_init (): This function is only called once after USB is started. This function mainly adds the initialization code of the USB data transfer, which is to be configured before transmission. With 68013 internal registers, the clock, FIFO, interrupt, etc. are configured.

void Td_poll (): User scheduler, USB repeatedly executes the function during idle time, usually putting code that executes repeatedly inside.

void isr_extr0 (void) Interrupt 0: External interrupt processing function, when the external interrupt is generated, the program jumps to this, executes the interrupt subroutine.

void Td_init (void)

1, set the CPU is 68013 clock 24MHZ. Set the clock register cpucs=0x0a, where the Cpucs register is as follows:


PORTCSTB---1 indicates that the rd# and wr# signals are generated when reading and writing port C, 0 does not generate read-write signals and defaults to 0.

clkspd1,clkspd0---CPU clock settings. As shown in the following table:

In the CC1601 capture card version, this register can be modified to the CMOS provided by the clock, 12M, 24M, 48M.

Note: The clock setting is too high and may cause the CMOS output to be unhealthy. Lowering the clock reduces the frame rate and increases stability.

CLKINV---clock State reversal

Clkoe---clock enable

2. Interface Configuration Register Ifconfig

Set ifconfig=0x03; Select as external clock, Sync Slavefifo mode, input//IFCLK (5-48mhz) (0000_0011)


IFCLKSRC---0 external clock source, 1 internal clock source.

3048mhz---0 ifclk clock is 30m,1 ifclk clock is 48M.

Ifclkoe---ifclk clock output enable, 0 off, 1 open.

Ifclkol---ifclk signal anyway, 0 not reversed, 1 reversed

Async---GPIF synchronous or asynchronous operation, 0 synchronous, 1 async

gstate---GPIF status output Enable, 0 off, 1 Enable, pin PE0 PE1 PE2 and GPIF status Gstate0,gstate1,gstate2.

IFCFG0,IFCFG1---Mode setting, which determines the port pin function.

3. REVCTL Chip Version Control register

Set revctl=0x03;


This register is used in slave FIFOs programming, it is recommended to set the b1b0=11.

4. Endpoint 1IN and 1OUT configuration registers

By the drive design, only the FIFO 2 is used. Therefore, these two registers directly with the default value, only for a brief introduction.

TYPE1,TYPE0---Endpoint types are shown in the table below.

5, Endpoint 2, 4, 6, 8 configuration register

Because only the endpoint 2 is used, the EP2CFG=0XE0 is set, and the EP2CFG register is shown below.

Valid---0 endpoint is invalid and the 1 endpoint is valid.

Dir---endpoint direction, 0=out direction, 1=in direction, default endpoint 2, 4 bit in, end 6,8 as out.

TYPE1,TYPE0---The endpoint type, as shown in the following table.

Size---buffer size (port 2 and endpoint 6 only), 0=512 bytes, 1=1024 bytes

BUF1,BUF0---The number of endpoint buffers (port 2 and endpoint 6 only).

Set it to endpoint 2 valid, in direction, bulk transfer mode, transmission byte 512B, four buffering mode.

The Ep4cfg, ep6cfg, and ep8cfg are set to invalid.

6. Slave FIFO endpoint 2/4/6/8 FIFO configuration

Set ep2fifocfg=0x08; indicates FIFO 8-bit input mode.

INFM1---1 indicates that the in endpoint is 1 full minus.

OEP1---1 indicates that the out endpoint is empty plus 1.

autoout---1 means that data is automatically submitted out of the endpoint fifo,0 represents manual.

Autoin---1 indicates that the in endpoint FIFO data is automatically submitted sie,0 represents manual.

Zerolenin---1 means enable 0 length in endpoint packet, 0 means non-enable.

wordwied---Data width, 0 means 8bit,1 represents 16bit.

For other FIFO, it is directly configured to 0x00 because it is useless.

7, set the SLWR is active high, the other is low-level active. Set by Portacfg and Fifopinpolar registers.


The Portacfg |=0x40 indicates that the SLCS is set to the multiplexed pin function and is active at low levels.


0 indicates low active

1 indicates active high level

Here Fifopinpolar = 0x07 The SLWR is set to high, the remaining settings are active low.

8. Endpoint 2 autoin data length setting

Set ep2autoinlenh = 0x02;//packet length high byte, auto transfer packet size is 512B.


9, Autoptrsetup |= 0x01;//Enable automatic pointer feature, it is convenient to transfer data between two memory.

10. SLAVE FIFOs FLAGX Configuration Register

Pinflagsab = 0x00;




This part is not included in the hardware driver, and is negligible.

11. Reset FIFO Register


Nakall---0 to turn off the Nak feature and 1 to respond to a master request with a nak. When resetting the endpoint, in order to ensure normal reset, to prevent the interference of the main controller request, first write to 0x80, after the reset is complete, and then write 0x00, in response to the request. As shown below:

Fiforeset = 0x80;//Activate Nak-all to avoid race conditions

Fiforeset = 0x02;//Reset, FIFO 2

Fiforeset = 0x04;//Reset, FIFO 4

Fiforeset = 0x06;//Reset, FIFO 6

Fiforeset = 0x08;//Reset, FIFO 8

Fiforeset = 0x00;//Deactivate Nak-al

12. Configuring 68013 Core Pins

As shown in the schematic, the USB_PA0 as the interrupt source, input to USB68013, set the usb_pa0 pin as the input pin. and usb_pd5 as Usb_trigger, output to the FPGA, can be considered to be 68013 to give the FPGA feedback signal. Therefore, the USB_PD5 is set to the output pin.

• Set the PD5 as the output pin in the program and initialize the PD5 to 0.

OED |= (1<<5);//pd5 0:input; 1:output

OED = 0x20;

PD5 = 0;

OED port D output enable register

• Set the PA0 as the interrupt trigger source in the program.

OEA Port A output enable register

Set the PA0 as the input pin, which is the default d0=0, and set the PA0 to external interrupt int0#.

OEA &= ~ (1<<0); Pa0-int0 0:input


Portacfg |= (1<<0); Configure PA0 as int0#

Portacfg = 0x01;

13. Special Function Register Tcon

A special function Tcon is adopted to set the int0# interrupt type. When It0=1, the rising edge is used to trigger the interrupt, and when it0=0, a low level trigger interrupt is used. Set ie=1 allow interrupt, ie=0 prohibit interrupt.

IT0 = 1; When ITx = 1, Posedge edge Sample; When ITx = 0, low-level//sample.

IE |= (1<<0);//enable INT0

Isr_extr0 (void) Interrupt 0

The interrupt processing of CB, can word: Draw frame. Due to the limitations of PC itself, in order to reduce the bandwidth of PC, the image of 640*480 pixel size obtained is processed by frame extraction. USB68013 only receives part of the image to effectively reduce the bandwidth of the PC. The process is as follows:

pa0 as the interrupt source, take the rising edge to trigger the interrupt, connect to the Cmos_vsync, that is, the camera field signal. The rising edge of the spot signal marks the end of a frame and the beginning of the next frame.

The frame_interval_en is the enable signal for the frame to be pumped, with an initial value of 1. Each time the interrupt is entered, the frame counter automatically adds 1, and the frame counter is determined to realize the frame processing.

The PD5 signal is a USB connection to the FPGA signal, by assign USB_WR = I2c_config_done & Cmos_href & Usb_trigger; it is known that USB allows data to be written when pd5=1.

• When Frame_cnt%2==0, write FIFO in 15FPS;

• When the condition frame_cnt%2==0 is met, the Pd5=1, which allows write FIFO, is not satisfied, pd5=0, the write FIFO is forbidden.

• Resets the FIFO 2 each time the write FIFO is blocked. So that the FIFO 2 data is empty so that there is no FIFO full state. This prevents data loss due to FIFO full state.

void Isr_extr0 (void) Interrupt 0//using 0


if (frame_interval_en = = 1)



if ((frame_cnt%2) ==0)//5:6fps; 4:7.5fps; 3:10fps; 2:15fps; 1:30fps;


PD5 = 1; Enable Image Input




PD5 = 0; Disable Image Input

Reset FIFO of EDP2


Fiforeset = 0x80;//Activate Nak-all to avoid race conditions


Fiforeset = 0x02;//Reset, FIFO 2


Fiforeset = 0x00;//Deactivate Nak-al






PD5 = 1; Enable image input continue, and no frame interval



USB2.0 High-speed video capture 68013A Register configuration instructions

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