Use dm9000 without OS

Does anyone use dm9000 without OS? [Recovery]
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[Landlord location] zchong
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From: Nanjing, China
Recently, dm9000 driver in ads is always unsuccessful. I wonder if anyone has performed operations on dm9000 without OS?

2008-09-25, 12: 46: 09

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[1st Floor] ql103
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From: Guilin
Recently I am also working on migrating the dm9000 driver to the linux2.6 kernel. I have no clue!

2008-09-25, 21: 40: 07

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[2 Floor] zchong
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When I debug in ads, I found that the read ID is always 0x46464646. Each time I read the dm9000 0x28 register content, somehow

2008-09-26,12: 31: 58

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[Third Floor] xiaoerge
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It seems that all the control registers of dm9000 are accessed by byte, and some data registers can be accessed by 16 bits.
I can send and receive packets in the lpc2200 environment.

2008-09-26,15: 31: 43

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[4th floor] zchong
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From: Nanjing, China
Can I send a copy of the driver, brother on the third floor?
Zchongnari@126.com

2008-09-26,17: 38: 43

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[5th Floor] zchong
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And so on

2008-09-27,12: 13: 42

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[6th Floor] zllfdd
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From: Luoyang, Henan Province
Uboot has a dm9000 driver. I don't know if uboot is an OS.

2008-09-27,12: 30: 34

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[7 th floor] xiaoerge
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I don't know much about the Internet. In fact, I can send and receive data as long as there is no problem with initialization. I don't know much about the Register of hash.
My board is from the lpc2220
//---------------------------------------------------------
# Define dm9000_addr 0x82000000
# Define dm9000_data 0x82000002
# Define dm9000write (ADD, dat) * (volatile unsigned short *) dm9000_addr) = add ;\
* (Volatile unsigned short *) dm9000_data) = dat
# Define dm9000read (ADD, dat) * (volatile unsigned short *) dm9000_addr) = add ;\
Dat = * (volatile unsigned short *) dm9000_data)
//---------------------------------------------------------
/*************************************** ****************************/
Void dm9000init (void)
{
Unsigned short I;
Dm9000write (0x1f, 0x00); // power up phy
Dm9000write (0x00, 0x01); // insert soft Reset
While (1)
{
Dm9000read (0x00, I );
If (I & 0x01) = 0)
{
Break;
}
}
Dm9000write (0x00, 0x00 );
Dm9000write (0xff, 0x81); // enable SRAM pointor auto return to start address
//-------------------------------------------------------------------
// Initiate phisical address
Dm9000write (0x15, 0x00); // 0x10-15 is phisical address
Dm9000write (0x14, 0x03 );
Dm9000write (0x13, 0x00 );
Dm9000write (0x12, 0x00 );
Dm9000write (0x11, 0x00 );
Dm9000write (0x10, 0x00 );
Dm9000write (0x1d, 0x00 );
Dm9000write (0x1c, 0x03 );
Dm9000write (0x1b, 0x00 );
Dm9000write (0x1a, 0x00 );
Dm9000write (0x19, 0x00 );
Dm9000write (0x18, 0x00 );
Dm9000write (0x17, 0x00 );
Dm9000write (0x16, 0x03 );
Dm9000write (0x01, 0x2c); // clear flag
// Dm9000write (0x23, 0x00); // tx sram read pointer address
// Dm9000write (0x22, 0x00 );
// Dm9000write (0x25, 0x0c); // rx sram read pointer address
// Dm9000write (0x24, 0x00 );
Dm9000write (0x32, 0x03); // enable receive checksum check
// Dm9000write (0x32, 0x00 );
// Dm9000write (0x2e, 0x18 );
// Dm9000write (0x2e, 0x00 );
Dm9000write (0x05, 0x6f); // enable receive
Dm9000write (0xfe, 0x3f); // clear all interrupt flag
Dm9000recvptr = 0x0c00;
Dm9000transptr = 0x00;
}
/*************************************** ****************************/
Unsigned short dm9000packetread (unsigned short * PTR)
{
Unsigned int I;
Unsigned short J;
Dm9000write (0xf4, dm9000recvptr); // write read address
Dm9000write (0xf5, (dm9000recvptr> 8); // write read address
* (Volatile unsigned short *) dm9000_addr) = 0xf0; // pre-fetch data
I = * (volatile unsigned short *) dm9000_data );
* (Volatile unsigned short *) dm9000_addr) = 0xf2;
I = * (volatile unsigned short *) dm9000_data); // head 0x01 and status
I = * (volatile unsigned short *) dm9000_data); // Byte Count
J = I-4;
Dm9000recvptr = dm9000recvptr + I + 4;
I = (I-3)> 1; // sub CRC length, odd Byte Count include
Do
{
* PTR = * (volatile unsigned short *) dm9000_data );
PTR ++;
}
While (-- I)> 0 );
Return (j );
}
/*************************************** ****************************/

2008-09-27,17: 25: 36

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[8 th floor] zchong
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From: Nanjing, China
To [6th Floor] zllfdd:
I proposed it from U-boot.
To [7 th floor] xiaoerge:
Thank you. Is there a read ID statement? I have also read the compilation of my programs. I haven't found any problems. Please take a look at the reasons.
This is my situation.
When reading the vid and PID, it is to read the 0x28-0x2b register of dm90000. My test program is:
Id_val = dm9000_ior (dm9000_vidl); id_val = 0x46
Id_val = dm9000_ior (dm9000_vidh); id_val = 0x46
Id_val = dm9000_ior (dm9000_pidl); id_val = 0x46
Id_val = dm9000_ior (dm9000_pidh); id_val = 0x46
If so:
// Id_val = dm9000_ior (dm9000_vidl );
Id_val = dm9000_ior (dm9000_vidh); id_val = 0x0a
Id_val = dm9000_ior (dm9000_pidl); id_val = 0x0a
Id_val = dm9000_ior (dm9000_pidh); id_val = 0x0a
If so:
// Id_val = dm9000_ior (dm9000_vidl );
// Id_val = dm9000_ior (dm9000_vidh );
Id_val = dm9000_ior (dm9000_pidl); id_val = 0x00
Id_val = dm9000_ior (dm9000_pidh); id_val = 0x00
Also:
// Id_val = dm9000_ior (dm9000_vidl );
// Id_val = dm9000_ior (dm9000_vidh );
// Id_val = dm9000_ior (dm9000_pidl );
Id_val = dm9000_ior (dm9000_pidh); id_val = 0x90
That is to say, the first read is correct, and the data read later is the same as the previous one. It feels like a problem occurs in a small place, but it cannot be found.

2008-09-28, 08: 23: 35

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[9th floor] stdio
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From: Shenzhen
Check the reset circuit of the dm9k. There is a problem with the direct power supply of the RST foot.

2008-09-28, 09: 44: 15

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[10th Floor] zchong
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From: Nanjing, China
To [9th floor] stdio:
Thank you. I will study it again.

2008-09-28, 12: 14: 06

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[11 th floor] ql103
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From: Guilin
The dm9000 driver was finally transplanted to linux2.6, But the strange thing is that you cannot Ping yourself.

2008-09-28, 12: 19: 07

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[Floor 12] zchong
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From: Nanjing, China
To [9th floor] stdio:
My RST pin is directly connected to Gnd. It should be okay, and the hardware should be okay, because it can be used in Linux.
[11 th floor] ql103:
I wonder if this middleware has tested dm9000 in ads, as long as it is in an environment without an operating system?

2008-09-28, 13: 10: 53

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Floor 13: am675

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From: CD
The problem is that the mmu_enabledcache function can be removed after data caching is enabled in the mmu_init function.
The principle is expected to be explained by experts
This post has been edited by am675. The last modification time is 2009-09-25, 16: 24: 10.

2009-09-25, 16: 23: 42

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Floor 14: am675

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The real reason has been found: In mmu_init, the corresponding address segment is opened and the corresponding cache is enabled. In this way, the CPU read/write operations will be performed in, resulting in the same results.
Solution:
In mmu_setmtt (0x20000000, 0x27f00000, 0x20000000, rw_cnb); // bank4 for dm9000
Change rw_cnb to rw_ncnb // cache_off and wr_buf to disable Cache

2009-09-25, 21: 26: 34

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[17 th Floor] ep1c3
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Thank you for your explanation. I encountered the same problem and solved it.

2010-04-25, 20: 14: 00

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[Floor 18] eworker
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Good