Use microblze (vivado version) in Embedded Design)

Original Xilinx official documentation ug898-vivado-embedded-design chapter 3

I. Introduction to microblze processor design (omitted)

2. Create an IP address design with a microblze Processor

Using vivado for microblze design is very different from using Ise. (Translator Jia: So you should take a closer look at the instructions below)

Vivado ide uses IP integrated design tools for embedded development. The IP comprehensive tool is an image-based interface tool that helps you build complex IP subsystems.

The IP directory of vivado ide provides many ready-made IP cores for use. You can also add custom IP cores to this directory.

 

Start IP integrated design (STEP)

1. Click IP integrator in the workflow navigation panel.Create block design.(You are about to build a block chart with an IP core)

2. Add IP address, find microblze, and add it to the block.

(Of course, you can also use the Tcl command to add the IP Core: create_bd_cell-type IP-VLNV xilinx.com: IP: microblze: 9.3 microblze_0)

3. Double-click the block of microblze to start configuring the soft core.

 

Iii. microblaze Configuration window (Configuration window description)

The Configuration Wizard provides the following functions:

--- One-click template-based configuration dialog box

--- Evaluation of the main parameters of microblze: relative area, frequency, performance, evaluation is based on the parameters specified in the dialog box.

--- Wizard for configuring the process

--- Prompts for all configuration options to understand the functions of each option

--- Use the adaanced button to directly access all the options of the Tabbed interface.

 

The following Wizard Page is provided in the microblaze Configuration Wizard:

--- Configuration Wizard: the first page provides Template Selection and general settings.

--- General: select and optimize the execution unit.

--- Exceptions: enables abnormal functions. (If this function is selected on the first page)

--- Debug: Number of breakpoints and viewing points. (If this function is selected on the first page)

--- Cache: cache settings. (If this function is selected on the first page)

--- Memory Management Unit (MMU): MMU settings. (If this function is selected on the first page)

--- Bus (buses): Bus settings. The last page is always displayed.

 

On the welcome page of the Configuration Wizard, the left side shows the relative evaluation of the current set frequency, area, and performance.

Frequency: this value is normalized using the maximum value of the current architecture to obtain the relative value. Indicates the frequency that the current setting can reach. (This value may exceed 30% than the actual value. Do not use this estimation value as a guarantee for the system to reach a certain frequency .)

Area: This value indicates the number of luts. It is normalized using the maximum value of the current architecture to obtain the relative value .... (... 5% ...)

Performance: the relative performance of the current settings.

Brams :( not found in vivado 2015.1)

Dsp48 or mult18: (not found in vivado 2015.1)

 

Page 1 (welcome page)

The simplest way to use the Configuration Wizard is to use one of the six configuration templates, each of which is a complete configuration solution. You can use the template as the starting point for your own configuration, and then modify the settings given by the template.

Every time you modify an option, the evaluation parameters on the left are updated in real time. The following describes the six configuration templates.

--- Minimum area: the minimum architecture provided by the soft core. No cache and debugging.

--- Maximum performance: the maximum possible performance. It has a large cache and debugging capacity and all execution units.

--- Maximum frequency: the highest possible frequency. Small cache, no debugging, part of the Execution Unit.

--- Linux with MMU (llinx with MMU): High-Performance settings can be obtained when running Linux with MMU. Memory Management Enabling, large cache and debugging, and all execution units.

--- Low-end Linux with MMU:... memory management enabling, small cache and debugging.

--- Typical: compromise between performance, area, and frequency. Suitable for offline programs with low overhead kernel. Provides caching and debugging functions.

 

General settings

If the template is not selected, you can configure options based on project requirements on the page. When you place the mouse over the option, a prompt will appear to tell you what it is. The following describes these options in detail.

--- Select implemention to optimize area (with lower instruction throughput): enables area optimization. If this is selected, implementation will optimize the area, especially reduce the number of pipelines, from 5 to 3. (Recommended: We recommend that you enable this option in a resource-tight architecture such as Artix-7. However, if you have performance-sensitive requirements, do not select this option, because some commands require additional clock cycles for execution. In addition, for MMU, branch target cache, instruction cache streams, instruction cache victims, data cache victims, and ACE, the area cannot be optimized .)

--- Enable microblaze debug module interface: enables debugging. Use Xilinx microprocessor debugger to download and Debug programs. (Recommended: Do not disable this function unless area resources are scarce .)

--- Use instruction and data caches: When executing a program outside LMB, you can use the command cache to improve performance. The command cache has the following features: when using external storage, activating this option can significantly improve performance, even if the cache is small.

--- Enable exceptions: You must activate this option when using an operating system that supports exceptions. Or add an exception callback function to a separate program.

--- Use memory management: to activate an operating system (such as Linux) that supports Virtual Memory protection. (When you enable area optimization or stack protection, the memory management unit is invisible and disabled automatically)

--- Enable discrete ports: enable independent ports on the soft core.

 

Page 2 (General)

1. commands (Instructions)

--- Enable Barrel Shifter. To activate this parameter, you can use the following command (bsrl, BSRA,...) to improve the application performance, but increase the size of the soft core. If activated, the compiler will automatically use the cylindrical locator command.

--- Enable floating point unit: enables a single precision Floating Point Unit (FPU ). FPU can significantly improve the single-precision floating point performance of applications and increase the size of soft cores.

--- Enable integer multiplier: Enable an integer multiplier hardware. If activated, you can use the Mul and Muli commands when assigning values to mul32. Use the mulh, mulhu, and mulhsu commands when assigning values to mul64. This parameter can be set to none, and Mul or dsp48 can be released for other purposes. This has little impact on the area of the soft core. When this option is used, the compiler automatically uses the Mul command.

--- Enable integer divider: Enable an integer splitter hardware. If activated, you can use the idiv and iduvu commands. Enabling this option improves division performance in applications, but increases the size of soft cores. When this option is used, the compiler automatically uses the idiv command.

--- Enable additional machine status register commands (enable additional machine status register instructions): If activated, you can read and write MSR and use msrset and msrclr commands. It can improve the performance of MSR access.

--- Enable pattern comparator: If it is activated, you can use the pattern matching command pcmpbf, pcmpeq, and pcmpne. The pattern match byte query command (pattern comparator byte find, pcmpbf) returns the location of the first byte to improve the efficiency of string and pattern matching operations. If enabled, the SDK library automatically uses this command. The pcmfeq and pcmpne commands return 1 or 0 based on whether the two words are the same. These commands increase the efficiency of setting flags and will be automatically used by the compiler. To activate this option, you can also run the Count leading zeros command clz. Clz instructions can improve the efficiency of priority encoding.

--- Enable reserved load/store and swap instructions commands: lbur, lhur, LWR, SBR, SHR, SWR, swapb, and swaph. These commands can read and write data in a byte order, and the switch command can exchange bytes or half characters in length. When you access the big-Endian network with the microblze of little-Endian, the efficiency can be improved.

--- Enable additional stream commands: provides additional functionality when using AXI4-Stream links. This includes the dynamic access commands getd and putd, which use registers to Select interfaces. (Important: You must activate the stream exception function to use these commands and select a stream link)

2. Optimization

Select implementation to optimize the area (when the command throughput is low): This option is the same as the option function on the welcome page ....

3. Fault Tolerance

--- Enable Fault Tolerance support)

 

Page 3 (exception)

1. Math exceptions)

--- Enable floating point unit exception

--- Exception in enable Integer Division

2. Bus exceptions)

--- The Axi on the enable command side is abnormal.

--- The Axi of the enable data segment is abnormal.

3. Other exceptions)

--- Abnormal enabling of invalid commands

--- Enable unaligned data to be abnormal

--- An invalid command exception occurs, except for the NULL command

--- Enable stream exception

--- Enable stack protection

 

Page 4 (cache)

Page 5 (MMU)

Page 6 (debugging)

Page 7 (bus)

1. Local memory bus interface (LMB)

2. Axi and ACE Interfaces

3. Stream interface

4. Other interfaces

 

Iv. Cross-trigger feature of microblze Processor

When Basic Debugging is enabled, the cross-trigger function provides two signals: dbg_stop and mb_halted.

--- When dbg_stop is input as 1, The microblze will be paused after several commands. Xmd detects that the microblze is paused and records the paused position. This signal can be used by any external event to pause the soft core, for example, when an integrated logical analyzer (ILA) is triggered.

--- The output signal of mb_halted is 1. When microblze is paused, for example, when a breakpoint or observation point is reached, an xmd Stop command is executed, or when dbg_stop is set to 1. When the soft core is restarted using the xmd command, the output is cleared by 0.

These two pins are hidden unless show discrete ports are displayed on the welcome page ).

 

You can also use the mb_halted signal to trigger an integrated logic analyzer, or suspend other microblze soft Cores (connected to their dbg_stop ends) in a multi-core system ).

When the extended debugging function is enabled, the cross-trigger function can be used with MDM. Mdm provides programmable cross-trigger functions in all connected processors, including the input and output of external triggers. You can view details in the microblaze debug module Product Guide.

Up to 8 cross-trigger actions are supported in microblze. The cross-trigger action is generated by the corresponding MDM cross-trigger output. The two are connected through the debug bus.

You can set the extended debugging function in two ways: one is the debugging configuration page mentioned above, and the other is to select this function when running the block antomation of microblze.

In addition, enable cross trigger is also enabled on the configuration page of the MDM module ). The MDM module can configure up to four sets of externally triggered inputs and outputs.

Finally, run connection automation to connect the cross-trigger signal to ILA (ILA tutorial ).

...

 

 

V. Custom Logic

The IP manager of vivado allows users and third-party IP address core developers to add custom IP addresses to the IP address core directory of vivado. In this way, you can instantiate a third-party IP Core in vivado.

When IP developers use vivado's IP manager to package IP cores, IP users have the same experience with Xilinx's IP cores, third-party IP addresses, or user-defined IP addresses.

IP developers can use the IP manager to package IP files and put the data into a zip file. The IP user receives the ZIP file, installs It In The vivado IP address directory, and then the user can use this IP address core.

Recommendation: To ensure the quality of the IP core, it is recommended that IP developers run each IP core in the user's workflow to ensure that each IP core is available.

 

 

6. Complete the connection)

After you have configured the microblze processor, you can start to instantiate other IP cores and continue your design.

On canvas, right-click and select Add IP.

You can use two built-in features to complete the IP core design for the remainder of the subsystem: block automation and conncetions automation, helping you place a basic microprocessor system, and/or connect the port to the external I/O port.

Block Automation

The block automation function can be used when block design instantiates a ipvq7 processing system or a microblze processor.

1. Click RUN block automation to help you complete a simple microblaze system.

The run block automation dialog box provides the basic features required by a microprocessor system.

2. Click OK.

Using connection Automation

When the IP integration tool finds a possible connection between IP address instantiation on the canvas, it will enable the connection automation function.

For example, I added two additional IP cores, gpio and uartlite. The IP integration tool determines the connection:

--- The ext_reset_in pin of the processor must be connected to a reset source. The reset source can be an internal reset source or an external input pin.

--- The clk_in_mongod pin of the clock module must be connected to an internal clock source or an external input pin.

--- The s_axi of Axi gpio must be connected to the Axi interface of a host.

--- The core gpio of the Axi gpio must be connected to an external Io pin.

--- The s_axi of uartlite must be connected to the Axi interface of a host.

--- Uartlite UART must be connected to the external pin.

 

Using board automation

When using a board like kc705, vivado provides board automation (like me, it's only a plug-in of nexys4, but it's only... angry)

 

 

Manual connections in an IP integrator Design

(Note: Generally, You can manually connect the connection, similar to the one in the sub-Software of the AD canvas)

Manual creating and connecting to I/O Ports

You can create an external I/O port in the IP address tool. You can select an I/O port from a signal or interface to an external port, and connect it by selecting a pin, bus, or interface.

The specific method is to right-click the pin interface of the module. In the pop-up menu, select:

--- Make external. You can use the multi-choice operation (CTRL + Click) to select multiple ports. This command is used to connect the pins on the module to the external pins.

Startgroup
Create_bd_intf_port-mode master-VLNV xilinx.com: interface: gpio_rtl: 1.0 gpio
Connect_bd_intf_net [get_bd_intf_pins axi_gpio_0/gpio] [get_bd_intf_ports gpio]
Endgroup

(This is the Tcl command for this operation. The first sentence is to create a port, and the second sentence is to connect)

 

--- Create port. This command is used for non-signal interfaces, such as clock, reset, or uart_txd. Many parameters can be set during creation, such as output/output, bit width, and type. For a clock, you must specify its frequency.

Startgroup
Create_bd_port-Dir I-type CLK AA
Set_property config. freq_hz 100000000 [get_bd_ports AA]
Endgroup

(This is the Tcl command for this operation. The first sentence is to create a port, and the second sentence is to set parameters)

 

--- Create interface port. This type of port is created for a group of signal interfaces of the same function. For example, s_axi is an interface port of some Xilinx IP addresses. This interface can also specify the interface type and mode (host or slave ).

 

Memory Mapping in address Editor

The method for generating address ing is as follows:

1. Click address editor.

2. Click auto assign address on the left. (The buttons are on the left)

If you do not generate the address for the first time when generating RTL code from the IP block diagram, a prompt box is displayed, providing an automatic Address allocation tool.

You can also set the address in the offset address and range fields. Address editor is enabled only when the IP address block diagram contains the IP core of a bus host (such as ipvq7.

 

Running design rule checks

Vivado checks design rules in real time. However, errors always occur. For example, the frequency on the clock pin may not be set correctly.

To run a comprehensive check, click Validate design.

 

Integrating a block design in the top-level design

After completing the above steps, there are two more steps to do:

--- Generate output file

--- Create an HDL Encapsulation

Create a file in the project source file window. The file type depends on whether the project is created in OpenGL or VHDL. The specific method is as follows:

1. on the block design panel, expand design source and select generate output products.

2. In the left-side workflow Panel, under the IP tool, click Generate block design.

You can integrate an IP block in a high-level design. In this way, the block design is instantiated in a high-level HDL file.

 

To instantiate a higher level, right-click design in design Sources on the block design panel and choose create HDL encapsulation.

Vivado provides two methods to create the HDL encapsulation:

--- Vivado creates and automatically updates the encapsulation. This is the default option.

--- Create a user-modifiable script that can be modified and saved. If you select this option, you need to modify the manual update encapsulation every time you modify the port in block design.

 

By now, you have designed the HDL encapsulation for your IP address, and you can proceed with the subsequent steps.

 

Restrictions on the microblaze Processor

When the IP tool generates an output file, it creates a constraint file for the IP core. However, you must set constraints for custom IP addresses or higher-level code.

A group of constraints is a set of constraints contained in the xdc file. There are two constraints:

--- Physical constraints. Pin placement, absolute or relative position of the Cell (Bram, LUT, flip flop), and device configuration are defined.

--- Time series constraints. Following SDC industry standards, the frequency requirements for design are defined. Without timing constraints, vivado only optimizes the line width and wiring congestion. (Without timing constraints, vivado implementation cannot improve the design performance. Vivado does not support UCF format constraints)

 

For the time series constraints, I would like to say a few more:

You have several ways to use the constraint set:

--- A collection contains multiple constraints.

--- Multiple constraint sets, but in separate folders.

--- A master constraint file. The changes in the design are stored in a new constraint folder.

---...

Separating constraint files by function helps you better grasp the constraint policy from the macro perspective and cope with changes in the timing and implementation process.

The constraints are too deep and important. For more information, see the official documentation. Vivado design suite User Guide: Using Constraints

 

When you have completed the design and constraints, you can now synthesize, implement, and generate bit streams.

Then, you can import the hardware to the SDK. The specific method is:

File-> export hardware for SDK. A dialog box is displayed, which provides some options. You can export hardware definitions and bit streams and open the SDK. Then you can write the software.

Alternatively, you can import the ELF File to vivado from the SDK.

Reprinted: http://blog.csdn.net/DuinoDu/article/details/46723181

Category: Xilinx microblaf

Use microblze (vivado version) in Embedded Design)