Use of Altera special pins (except for the full range of Altera Fpga,msel differences)

Original address: http://group.chinaaet.com/99/47264

1.i/o, ASDO
In the as mode is a dedicated output pin, in PS and JTAG mode can be used when the I/O foot. In the as mode, the foot is the CII that sends a control signal to the serial configuration chip. It is also used to read configuration data from the configuration chip of the foot. In the as mode, the ASDO has an internal pull-up resistor that has been in effect until the configuration is complete and the foot becomes a tri-state input pin. The ASDO foot is directly connected to the ASDI foot (5th foot) of the configuration chip.
2.I/O,NCSO
In the as mode is the dedicated output pin, which can be used when the I/O pin is in PS and Jtag mode. In the as mode, this foot is the enable pin that CII uses to send to the external serial configuration chip. In the as mode, the ASDO has an internal pull-up resistor that has been in effect. This foot is active at low level. Directly to the/cs foot (1th foot) of the configuration chip.
3.i/o,crc_error
When the error detection CRC circuit is selected, the foot is used as the crc_error foot, if not the default to do I/O. However, it is important to note that this foot does not support open-drain and reverse. When it is crc_error, the high output indicates a CRC checksum error (an error occurred while configuring the SRAM bits). The support of the CRC circuit can be added in the setting. This foot is generally used in conjunction with nconfig feet. That is, if the configuration process fails, reconfigure.
4.i/o,clkusr
When the Enable user-supplled start-up clock (CLKUSR) option is turned on in the software, the foot is only available as a user-supplied initialization clock input pin. After all configuration data has been received, the conf_done foot becomes high, the CII device also requires 299 clock cycles to initialize registers, I/O and so on, the FPGA has two ways, one is to use the internal crystal oscillator (10MHZ), the other is from the CLKUSR The incoming clock (max. 100MHz). This feature slows down the time that the FPGA will start to work and can be used in special applications that require synchronization with other devices.
5.i/o,vref
Used to provide a reference level for certain differential standards. If it is not used, it can be used as I/O.
6. DATA0
Dedicated input feet. In the as mode, the configuration process is: CII will NCSO low level, configuration chip is enabled. CII then works with DCLK and ASDO, sending commands to the operation, and reading the address to the configuration chip. The configuration chip then sends data to CII via the data pin. The DATA foot is attached to the DATA0 foot of the CII. After the CII receives all the configuration data, it releases the conf_done foot (i.e. not forcing the conf_done foot low) and the Conf_done foot is open-drain (open-drain). At this point, because the conf_done is externally connected with a 10K resistor, it becomes high. At the same time, CII stops DCLK signals. After the conf_done becomes high (and then it becomes an input pin), the initialization process begins. Therefore, conf_done this foot outside must take a 10K resistor, to ensure that the initialization process can start correctly. The DATA0,DCLK,NCSO,ASDO has a weak pull-up resistor on the foot and is always active. After the configuration is complete, these pins become input tri-states and are set to high level by the internal weak pull-up resistor. In the as mode, the DATA0 receives the data (2nd foot) of the configuration chip.
7. DCLK
PS mode is input, as mode is output. In PS mode, the DCLK is a clock input pin that is the clock that the external device transmits the configuration data to the FPGA. The data is on the rising edge of the DCLK data, in the as mode, the DCLK foot is a clock output pin that is provided with a configuration clock. Directly to the configuration chip dclk foot up (6th foot). Regardless of the configuration mode, the foot becomes tri-state when the configuration is complete. If the external configuration device is configured, the device is configured to place the DCLK pin low. If you are using a master chip, you can set the DCLK high or the DCLK low. When the configuration is complete, triggering the foot does not affect the configured FPGA. This pin has input buffer, which supports the hysteresis function of Schmitt trigger.
8. NCE
Dedicated input feet. This foot is a low-active chip-selectable enable signal. The NCE foot is configured to enable the foot. In configuration, initialization, and user mode, the NCE foot must be low. During the configuration of multiple devices, the first device's nce foot is lowered, and its nceo is connected to the next device's nce foot, forming a chain. The nce foot is also required to lower the nce foot in JTAG programming mode. This pin has input buffer, which supports the hysteresis function of Schmitt trigger.
9. Nconfig
Dedicated input pins. This pin is a configuration control input foot. If the foot is lowered in user mode, the FPGA loses its configuration data, enters a reset state, and resets all the I/O pins to tri-state. The process of nconfig from low-level to high-level will initialize the reconfiguration process. If the configuration scheme uses an enhanced configuration device or EPC2, the user can connect the nconfig pin directly to VCC or to the ninit_conf foot of the configuration chip. This pin has input buffer, which supports the hysteresis function of Schmitt trigger. In fact, in user mode, the nconfig signal is used to initialize the reconfiguration. When the nconfig foot is lowered, the initialization process begins. When the nconfig foot is lowered, the CII is reset and enters the reset state, the Nstatus and conf_done feet are lowered, and all the I/O feet enter the tri-state. The nconfig signal must remain at least 2us. When the nconfig is back on the high level, the Nstatus is released again. The reconfiguration begins. In the actual application process, the Nconfig pin can be connected to a 10K pull-up resistor to 3.3V.
Ten. Dev_oe
I/O foot or global I/O enable foot. In the Quartus II software you can enable the Dev_oe option (enable device-wideoutput enable), if this function is enabled, the foot can be the global I/O enable foot, the function of this foot is, if it is low, all I/O are in the tri-state.
Init_done.
I/O foot or open-drain output pin. When the foot is enabled, the jump from low to high on the foot indicates that the FPGA has entered the user mode. If the Init_done output PIN is enabled, after the configuration is complete, the foot cannot be used as user I/O. Inside the quartusii can be enabled by enabling the Enable Init_done Output option to enable this foot.
Nceo.
I/o foot or output pin. When the configuration is complete, the foot outputs a low level. During the configuration of multiple devices, the foot is connected to the nce foot of the next device, which also requires a 10K pull-up resistor outside to Vccio. During the configuration of multiple devices, the Nceo of the last device can float. If you want to use this foot as a usable I/O, you need to set it up in the software. In addition, even if you do I/O, you have to wait until the configuration is complete.
Nstatus.
This is a dedicated configuration state foot. Two-way foot, when it is output foot, is open drain. After power-up, the FPGA immediately resets the nstatus foot to a low level, and after the reset (POR) is complete, release it and set it to high. As the status output pin, if any error occurs during the configuration process, the nstatus foot will be lowered. As the status input pin, during configuration or initialization, the external control chip can pull the foot low, the FPGA will enter the wrong state. This foot cannot be used as a normal I/O pin. The nstatus foot must pull up a 10K ohm resistor.
Conf_done.
This is a dedicated configuration state foot. Two-way foot, when it is output foot, is open drain. When the pin is output as a status, it is set to low level before and during the configuration. Once the configuration data is received and there are no errors, the initialization cycle starts and the Conf_done is released. When entering a pin as a state, when all data is received, it is set to high. The device then starts to initialize and then enters user mode. It cannot be used as normal I/O. This foot must also be connected to a 10K ohm resistor.
msel[1:0]
These feet are connected to a 0 or power supply, indicating high or low levels. 00 means using as mode, 10 for PS mode, and 01 for fast as mode. If Jtag mode is used, the JTAG mode has nothing to do with Msel, that is, with Jtag mode, Msel is ignored, but because they cannot float, it is recommended to receive it.
DEV_CLRN
I/O or global clear 0 input. In Quartusii, if you select the Enable Device-wide Reset (DEV_CLRN) function. This foot is the global clear 0 end. When the foot is lowered, all registers will be zeroed out. This foot does not affect the JTAG boundary scan or the programmed operation.

Use of Altera special pins (except for the full range of Altera Fpga,msel differences)