Use of generated statements (generate) in Verilog __verilog basics

One: Generate
Verilog-2001 adds a generate loop that allows multiple instantiations of module and primitive, as well as multiple variable,net,task,function,continous assignment, Initial and always. In generate statements, if-else and Case statements can be introduced and different instantiations are produced according to different conditions.
Usage:
1. Generate syntax has generate for, genreate if and generate case three
2. Generate for statement must have GENVAR keyword definition for variable
3. For content must add begin and end
4. A name must be given to the for phrase
Example:
1. Generate For example:
Generate
Genvar i; Generate 8 SAMLL FIFO for In_data[i] 8x72
For (i=0 i<num_queues; i=i+1) begin:in_arb_queues//num_queues = 8
Small_fifo
#( . WIDTH (Data_width+ctrl_width),
. Max_depth_bits (2))
In_arb_fifo
(//Outputs
. dout ({fifo_out_ctrl[i], fifo_out_data[i]}),
. Full (),
. Nearly_full (Nearly_full[i]),
. Prog_full (),
. Empty (Empty[i]),
Inputs
. DIN ({in_ctrl[i], in_data[i]}),
. Wr_en (In_wr[i]),
. Rd_en (Rd_en[i]),
. Reset (reset),
. CLK (CLK));
End//Block:in_arb_queues
Endgenerate
2.generate If example:
Generate
if (reg_width = = write_width) begin:new_data_a_generation
Assign new_data_a = merge_update? merge_wr_data:held_wr_data_a;
End
ELSE begin
Assign new_data_a = merge_update?
{{(reg_width-write_width-1) {merge_wr_data_sign}}, Merge_wr_data}:
{{(reg_width-write_width) {held_wr_data_sign_a}}, held_wr_data_a};
End
Endgenerate
3.generate can also perform multiple assign assignments.
Module Anytest_v (
Input CLK,
INPUT[7:0] DataIn,
OUTPUT[7:0] Dataout,
Output finish
);
WIRE[7:0] mem[31:0];
WIRE[32*8-1:0] XXX;
REG[7:0] I;
Generate
Genvar i;
for (i=0;i<=31;i=i+1)
Begin:wiertech
Assign mem[i]= 8 ' B0;
End
Endgenerate
Endmodule
PS: for A[8*i+:8]
This is the so-called "Indexed vector part selects"
In Verilog-1995, you can select either output of a vector or several successive outputs of a vector, but at this point the index of a number of successive values is constant. In Verilog-2001, you can use a variable as index to perform part select.
[base_expr +: width_expr]//positive offset
[base_expr-: width_expr]//negative offset
Where base_expr can be a variable, and width_expr must be a constant. +: Indicates that the WIDTH_EXPR bit is increased by base_expr,-that is, decreasing the width_expr bit by the base_expr up. For example:
reg [63:0] word;
reg [3:0] byte_num; A value from 0 to 7
Wire [7:0] Byten = word[byte_num*8 +: 8];
If the value of Byte_num is 4, word[39:32] is assigned to Byten
Second, the parameter passes
Similar to VHDL generic statements, Verilog can also be passed in the case of parameters
The passed parameter is the parameter defined in the child module.
Methods to pass:
1, Module_name # (Parameter1, Parameter2) inst_name (PORT_MAP);
2, Module_name # (. Parameter_name (Para_value),. Parameter_name (Para_value)) Inst_name (port map);
With the # method and the port map.
Module multiplier (A, B, product);
Parameter A_width = 8, b_width = 8;
Localparam product_width = a_width+b_width;
input [a_width-1:0] A;
input [b_width-1:0] b;
Output[product_width-1:0]product;
Generate
if ((A_width < 8) | | (B_width < 8))
Cla_multiplier # (A_width, B_width) U1 (A, B, product);
Else
Wallace_multiplier # (A_width, B_width) U1 (A, B, product);
Endgenerate
Endmodule