Verilog analysis of multiple blocking assignments occurring simultaneously with a single Reg variable

1 Modulemain ();2 Reg[5:0] A=0;3 Reg[5:0] B=0;4 Regclk=0;5 6  always@ (CLK)7 begin8a<=a+3;9b<=b+1;Ten End One  A  always@ (b) - begin -a<=a+2; the End -  -  always# -clk=~CLK; - Endmodule

See what the above output is?

Take a look at this piece of code:

1 Modulemain ();2 Regclk=0;3 Reg[5:0] A=0;4 Reg[5:0] B=0;5 6  always@ (CLK)7 begin8a<=a+3;9b<=b+1;Ten End One  A  always@ (b) - begin -a<=a+2; the End -  -  always# -clk=~CLK; - Endmodule

The difference is only in the line, the output of the result:

The reason is:

• If multiple blocking assignments are fired at the same time on the same reg variable, only the last one will be executed.
• In addition to blocking assignment statements, the other statements are executed sequentially.

If the above <= are changed to = that the nature of each trigger will be executed, this is a good understanding.

But if the trigger a changes the same signal (that must be at the same time), it depends on who is behind the position:

1' Timescale 1ns/1ps2 Modulemain ();3 Regclk=0;4 Reg[5:0] A=0;5 6  always# -clk=~CLK;7 8  always@ (CLK)9 beginTena<=a+3; One End A  -  always@ (CLK) - begin thea<=a+2; - End -  - Endmodule +  

1' Timescale 1ns/1ps2 Modulemain ();3 Regclk=0;4 Reg[5:0] A=0;5 6  always# -clk=~CLK;7 8  always@ (CLK)9 beginTena<=a+2; One End A  -  always@ (CLK) - begin thea<=a+3; - End -  - Endmodule

However, it is easy to avoid situations where multiple assignments of the same variable are not possible.

Verilog analysis of multiple blocking assignments occurring simultaneously with a single Reg variable