Verilog common system functions and examples

1. Open File

Integer file_id;

file_id = fopen ("File_path/file_name");

2. Write file: $fmonitor, $fwrite, $fdisplay, $fstrobe

$fmonitor keep recording as long as there's a change.

$fmonitor (file_id, "%format_char", parameter);

$fmonitor (file_id, "%m:%t in1=%d o1=%h", $time, in1, O1);

$fwrite need a trigger condition to log

$fwrite (file_id, "%format_char", parameter);

$fdisplay need a trigger condition to log

$fdisplay (file_id, "%format_char", parameter);

$fstrobe ();

3. Read files: $fread

Integer file_id;

file_id = $fread ("File_path/file_name", "R");

4. Close file: $fclose

$fclose (fjile_id);

5. Set the memory value of the file: $READMEMH, $readmemb

$READMEMH ("file_name", Memory_name "); Initialize data to hexadecimal

$readmemb ("file_name", Memory_name "); Initialize data to Binary

6. File display: $monitor, $write, $display

$display, $write for output information

$display ("Rvel =%h hex%d decimal", rvel,rvel);

$monitor ($time,, "rxd =%b Txd =%b", Rxd, Txd)

6. Document Location

$fseek, file location, can be manipulated from any point to the file;

$FSCANF to read and write to a file line.

7. Exit Emulator $finish

8. Random Data generation: $random

Here are some common applications:
1. Read and Write files
' Timescale 1 NS/1 NS
Module FILEIO_TB;
Integer fp_r, fp_w, CNT;
reg [7:0] reg1, REG2, reg3;
Initial begin
Fp_r = $fopen ("Data_in.txt", "R");
Fp_w = $fopen ("Data_out.txt", "w");

while (! $feof (fp_r)) begin
CNT = $FSCANF (Fp_r, "%d%d%d", REG1, REG2, reg3);
$display ("%d%d%d", REG1, REG2, reg3);
$fwrite (Fp_w, "%d%d%d\n", Reg3, REG2, REG1);
End

$fclose (Fp_r);
$fclose (FP_W);
End
Endmodule
2.
integer file, char;
Reg EOF;
Initial begin
File = $fopenr ("MyFile.txt");
EOF = 0;
while (EOF = = 0) begin
char = $fgetc (file);
EOF = $feof (file);
$display ("%s", char);
End
End
3. Document processing and positioning
' Define Seek_set 0
' Define Seek_cur 1
' Define Seek_end 2
Integer file, offset, position, R;
R = $fseek (file, 0, ' Seek_set);
R = $fseek (file, 0, ' seek_cur);
R = $fseek (file, 0, ' seek_end);
R = $fseek (file, Position, ' seek_set);
4.
Integer r, file, start, count;
reg [15:0] mem[0:10], R16;
R = $fread (file, mem[0], start, count);
R = $fread (file, R16);
5.
integer file, position;
Position = $ftell (file);
6.
Integer file, R, a, B;
reg [80*8:1] string;
File = $fopenw ("Output.log");
R = $sformat (String, "formatted%d%x", A, b);
R = $sprintf (String, "formatted%d%x", A, b);
R = $fprintf (file, "formatted%d%x", A, b);
7.
Integer file, R;
File = $fopenw ("Output.log");
R = $fflush (file);
8.
This is a pattern file-read_pattern.pat
Time Bin Dec hex
10:001 1 1
20:010 20 020
50.02:111 5 FFF
62.345:100 4 Deadbeef
75.789:xxx 2 zzzzzzzz
' Timescale 1NS/10 PS
' Define EOF ' hffff_ffff
' Define NULL 0
' Define Max_line_length 1000

Module Read_pattern;
Integer file, c, R;
reg [3:0] bin;
reg [31:0] Dec, hex;
Real Real_time;
reg [8* ' max_line_length:0] line;

Initial
Begin:file_block
$timeformat ( -9, 3, "NS", 6);
$display ("Time Bin decimal hex");
File = $fopenr ("Read_pattern.pat");
if (file = = ' NULL)//If error opening file
Disable File_block; Just quit

c = $fgetc (file);
while (c! = ' EOF)
Begin

if (c = = "/")
R = $fgets (line, ' max_line_length, file);
Else
Begin
Push the character back to the file then read the next time
R = $ungetc (c, file);
R = $fscanf (file, "%f:\n", real_time);

Wait until the absolute time in the file and then read stimulus
if ($realtime > Real_time)
$display ("Error-absolute time in file was out of order-%t",
Real_time);
Else
# (real_time-$realtime)
R = $fscanf (file, "%b%d%h\n", Bin,dec,hex);
End//If C else
c = $fgetc (file);
End//While not EOF

R = $fcloser (file);
End//Initial

Display changes to the signals
Always @ (bin or dec or hex)
$display ("%t%b%d%h", $realtime, Bin, Dec, hex);

Endmodule//Read_pattern
9. Automatic comparison of output results
' Define EOF ' hffff_ffff
' Define NULL 0
' Define Max_line_length 1000
module compare;
Integer file, R;
Reg A, B, expect, clock;
Wire out;
reg [' max_line_length*8:1];
Parameter cycle = 20;

Initial
Begin:file_block
$display ("Time Stim Expect Output");
Clock = 0;

File = $fopenr ("Compare.pat");
if (file = = ' NULL)
Disable File_block;

R = $fgets (line, max_line_length, file); Skip comments
R = $fgets (line, max_line_length, file);

while (! $feof (file))
Begin
Wait until rising clock, read stimulus
@ (Posedge clock)
R = $fscanf (file, "%b%b%b\n", A, b, expect);

Wait just before the end of cycle to do compare
# (CYCLE-1)
$display ("%d%b%b%b%b", $stime, A, B, expect, out);
$strobe _compare (expect, out);
End//While not EOF

R = $fcloser (file);
$stop;
End//Initial

Always # (CYCLE/2) clock =!clock; Clock Generator

and #4 (out, A, b); Circuit under test
Endmodule//Compare
10. Read data from a file to mem (this seems to be the most common use of people)
' Define EOF ' hffff_ffff
' Define Mem_size 200_000
Module Load_mem;
integer file, I;
reg [7:0] mem[0: ' mem_size];
reg [80*8:1] file_name;
Initial
Begin
file_name = "Data.bin";
File = $fopenr (file_name);
i = $fread (file, mem[0]);
$display ("Loaded%0d entries \ n", i);
i = $fcloser (file);
$stop;
End Endmodule//Load_mem

Verilog common system functions and examples