Verilog HDL Those things _ Modeling notes (experiment Three: Button shake)

Experiment Three: Button shake

First, the key shake function is divided into two modules, level check module and 10ms delay module. The level detection module is used to detect the change of the key signal (whether or not it is pressed),the10ms delay module is used to stabilize the input of the level check module, thereby stabilizing the key signal to prevent its jitter and the resulting signal jumps and affect the output.

Design ideas:

1. When the level detection module checks that the key is pressed (the input is changed from high to low), pull the high H2l_sig level and then pull down.

2.10MS delay module, the h2l_sig High level is detected, it is 10ms filtered, pull high output.

3. When the key is released, the level detection module pulls up the l2h_sig level and then pulls it down.

4.10MS delay module, the l2h_sig High level is detected, it is 10ms filtered, pull down the output.

Level detection module:

1. Need a 100us counter to detect the level of input, when the input level signal duration equals 100us, the level detection module receives the input of this signal, and then gives the corresponding output signal, This requires the definition of an enable signal isEn, control the output of the entire level detection module, when the input level signal duration to meet the requirements, theisEn signal is set, the level detection module output is enabled, Since the counter module is not used to generate a fixed time, the value of the counter can not be reset while the output of the level detection module is enabled.

2. The level detection module is initialized, because the function of the level detection module is to monitor the level of the signal jumps, therefore, the level of the change requires two signals to determine.

High level to low level:

H2L_F1 stores the current input pin level signal pin_in;

The H2l_f2 stores The level signal of the H2L_F1 pin, which is the level signal pin_in the previous time period.

Through the operation of these two signals (h2l_f1,h2l_f2), we get the calculation of the input signal from the high to low level of the transition condition , The output of the level detection module is then directly reflected.

Time	H2l_f1	H2l_f2	H2l_sig
Initial	1	1	0 (initialization, the input pin has no level change, this signal result is 0)
T1	0	1	1 (The result of this signal is 1) (the level changes from high level to low level)
T2	0	0	0 (the input pin level continues low, the input signal does not jump from high to low, this signal result is 0)

deduced:h2l_sig= (! H2L_F1) &H2L_F2;

Low level to High level:

L2H_F1 stores the current input pin level signal pin_in;

The L2h_f2 stores The level signal of the L2H_F1 pin, which is the level signal pin_in the previous time period .

Through the operation of these two signals (l2h_f1,l2h_f2), we get the input signal from the low level to the high level of the transition condition of the calculation formula , The output of the level detection module is then directly reflected.

Time	L2h_f1	L2h_f2	L2h_sig
Initial	0	0	0 (initialization, the input pin has no level change, this signal result is 0)
T1	1	0	1 (The result of this signal is 1) (The level changes from low level to high level)
T2	1	1	0 (The input pin has a high level and the input signal does not jump from low to high, then this signal results in 0)

deduced:l2h_sig=l2h_f1& (! L2H_F2);

10ms Delay module:

    1. 10ms 1ms+10ms architecture, That is, the counter is used to produce the standard 1ms, Span style= "FONT-FAMILY:CALIBRI;" >1ms 10ms counter plus 1 , equivalent to a carry. With the previous control led Light Unlike this, this counting module introduces a iscount

2.case structure, my understanding of cases module: usually used in multi-input modules, need to deal with a lot of situations, but the processing method of each case is clear, fixed. in the case structure, usually (case0:) as a selection, similar to the menu, it leads to other case (Case1:,case2:,casen :) entrance , and I also realize that the advantage of using this structure is that each time you execute another case (case1:,case2:,casen:), you can set Case (i), i=0 to reset it back to the original selection mode.

Verilog HDL Those things _ Modeling notes (experiment Three: Button shake)