Verilog HDL 4*4 Matrix Keyboard Scanning Program

The hardware circuit diagram is as follows:

1module Key
2
3 (
4
5 CLK,//50mhz
6
7 Reset,
8
9 row,//Line
10
One col,//column
12
Key_value//Key value
14
15);
16
17input Clk,reset;
18
input [3:0] row;
20
Output [3:0] col;
22
Output [3:0] key_value;
24
25
reg [3:0] col;
27
reg [3:0] key_value;
29
reg [5:0] count; Delay_20ms
31
reg [2:0] state; Status flag
33
Key_flag reg; Key sign Bit
35
Reg Clk_500khz; 500KHZ Clock Signal
37
reg [3:0] Col_reg; Register Scan column Values
39
reg [3:0] Row_reg; Register Scan Row values
41
42
43always @ (Posedge CLK or Negedge reset)
44
if (!reset) begin clk_500khz<=0; count<=0; End
46
Or else
48
Begin
50
An if (count>=50) begin Clk_500khz<=~clk_500khz;count<=0;end
52
/Else count<=count+1;
54
End
56
57
58
Always @ (Posedge clk_500khz or Negedge reset)
60
if (!reset) begin col<=4 ' B0000;state<=0;end
62
Or else
64
The Begin
66
Case (state)
68
69 0:
70
The Begin
72
Col[3:0]<=4 ' b0000;
74
Key_flag<=1 ' B0;
76
(row[3:0]!=4 ' b1111) begin state<=1;col[3:0]<=4 ' b1110;end//key pressed, scan first line
78
state<=0; Else
80
Bayi End
82
83 1:
84
The Begin
86
if (row[3:0]!=4 ' b1111) begin state<=5;end//judge whether it is the first line
88
Or else begin state<=2;col[3:0]<=4 ' b1101;end/scan the second line
90
The end
92
93 2:
94
The Begin
96
The IF (row[3:0]!=4 ' b1111) begin state<=5;end//Determine whether the second line
98
Or else begin state<=3;col[3:0]<=4 ' b1011;end/scan third line
100
The end
102
103 3:
104
The Begin
106
(row[3:0]!=4 ' b1111) begin state<=5;end//judge whether it is line 31st
108
109 Else begin state<=4;col[3:0]<=4 ' B0111;end/scan line Fourth
110
End
112
113 4:
114
The Begin
116
117 if (row[3:0]!=4 ' b1111) begin state<=5;end//Determine whether the first line
118
119 Else state<=0;
120
121 End
122
123 5:
124
The Begin
126
127 if (row[3:0]!=4 ' b1111)
128
129begin
130
131 col_reg<=col; Save Scan column Values
132
133row_reg<=row; Save Scan Row values
134
135state<=5;
136
137key_flag<=1 ' B1; With key pressed
138
139 End
140
A.
142
143 Begin State<=0;end
144
145 End
146
147 Endcase
148
149 End
150
151
152
153 always @ (clk_500khz or Col_reg or Row_reg)
154
The Begin
156
157 if (Key_flag==1 ' B1)
158
159 begin
160
161 case ({Col_reg,row_reg})
162
163 8 ' b1110_1110:key_value<=0;
164
165 8 ' b1110_1101:key_value<=1;
166
167 8 ' b1110_1011:key_value<=2;
168
169 8 ' b1110_0111:key_value<=3;
170
171
172
173 8 ' b1101_1110:key_value<=4;
174
175 8 ' b1101_1101:key_value<=5;
176
177 8 ' b1101_1011:key_value<=6;
178
179 8 ' b1101_0111:key_value<=7;
180
181
182
183 8 ' b1011_1110:key_value<=8;
184
185 8 ' b1011_1101:key_value<=9;
186
187 8 ' b1011_1011:key_value<=10;
188
189 8 ' b1011_0111:key_value<=11;
190
191
192
193 8 ' b0111_1110:key_value<=12;
194
195 8 ' b0111_1101:key_value<=13;
196
197 8 ' b0111_1011:key_value<=14;
198
199 8 ' b0111_0111:key_value<=15;
200
201 Endcase
202
203 End
204
205 End
206
207 Endmodule
208