VHDL common grammatical structure, paste here for easy query

Translated from: http://blog.sina.com.cn/s/blog_72cd3a5c01014wl1.html

A VHDL program code contains entities (entity), struct (architecture), Configuration (config), package, library , etc.

First, the data type

1. User-defined data types

Use the keyword type, for example:

TYPE My_integer is RANGE-32 to 32;

– Subset of user-defined integer types

TYPE Student_grade is RANGE 0 to 100;

– Subset of user-defined natural number types

TYPE State is (idle, forward, backward, stop);

– Enumeration data types, commonly used for state definitions of finite state machines

In general, data for enumerated types is automatically encoded sequentially.

2. Sub-type

You can define subtypes of a data type by adding constraints on the original defined data type . VHDL does not allow different types of data to operate directly, and a subtype of a data type can operate directly with the original type of data.

The subtype definition uses the subtype keyword.

3. Arrays (Array)

An array is a new type of data that sets together data of the same data type.

TYPE Type_name is ARRAY (specification) of data_type;

– Define a new array type syntax structure

SIGNAL Signal_name:type_name [: = Initial_value];

– Declaration of Signal,constant, variable using the new array type

For example:

TYPE Delay_lines is ARRAY (L-2 Downto 0) of signed (w_in-1 Downto 0);

– Filter input delay chain type definition

TYPE coeffs is ARRAY (L-1 Downto 0) of signed (w_coef-1 Downto 0);

– Filter factor type definition

SIGNAL Delay_regs:delay_lines; – Signal Delay Register Declaration

CONSTANT coef:coeffs: = (); – Constant coefficient declaration and assignment of initial value

4. Port array

When defining an input/output port for a circuit, it is sometimes necessary to define a port as a vector array, and type definition is not allowed in entity, so a user-defined data type must be established in the package set based on the specific signal characteristics of the port. This data type can be used for the entire design, including entity.

————————————— Package ———————————-

Library IEEE;

Use Ieee.std_logic_1164.all;

——————————————

Package My_data_types is

TYPE Vector_array is array (natural range <>) of Std_logic_vector (7 Downto 0); – declares an array of 8 bits

END my_data_types;

——————————— –main Code —————————————

Library IEEE;

Use Ieee.std_logic_1164.all;

Use Work.my_data_types.all; – User-defined package set

——————————————————————

ENTITY Mux is

PORT (Inp:in vector_array (0 to 3);

END Mux;

——————————————————————————-

5. Signed number and unsigned number

To use signed and unsigned type data, you must declare the package set Std_logic_arith in the IEEE Library at the beginning of the code. They support arithmetic operations but do not support logical operations .

Library IEEE;

Use Ieee.std_logic_1164.all;

Use Ieee.std_logic_arith.all;

......

SIGNAL A:In signed (7 Downto 0);

SIGNAL B:in signed (7 Downto 0);

SIGNAL X:in signed (7 Downto 0);

......

V <= A + b;

W <= A and B; – Illegal (logical operation not supported)

——————————————————————————-

Data of the Std_logic_vector type cannot be directly arithmetic, only the std_logic_signed and std_logic_unsigned two package sets are declared to perform arithmetic operations just like the data of the signed and unsigned types.

6. Data type Conversion

Many data type conversion functions are available in the Std_logic_arith package set in the IEEE Library:

1. Conv_integer (p): Converts the operand p of the data type Integer,unsigned,signed,std_ulogic or Std_logic to an integer type. does not contain std_logic_vector.

2. Conv_unsigned (p,b): Converts the operand p of the data type integer,unsigned,signed or std_ulogic to unsigned type data with a bit width of B.

3. Conv_signed (p,b): Converts the operand p of the data type to Integer, UNSIGNED, signed, or std_ulogic to data of type signed with a bit width of B.

4. Conv_std_logic_vector (P, b): Converts the operand p of the data type to Integer, UNSIGNED, signed, or std_logic to data of type std_logic_vector with a bit width of B.

Second, operator and attribute

1. Arithmetic operators

L Assignment operator

Assignment operators are used to assign values to signals, variables, and constants.

<= is used to assign values to the signal type;

: = used to assign values to variable,constant and generic, or to assign an initial value;

= = is used to assign values to certain bits in the vector, or to assign values to bits other than some bits (commonly used others).

Cases:

SIGNAL x:std_logic;

VARIABLE y:std_logic_vector (3 Downto 0); – The leftmost bit is the MSB

SIGNAL w:std_logic_vector (0 to 7); – The rightmost bit is the MSB

x <= ' 1 ';

Y: = "0000";

W <= "1000_0000"; The –LSB bit is 1 and the remaining bits are 0

W <= (0 = ' 1 ', OTHERS = ' 0 '); The –LSB bit is 1, the other bit is 0

L Logical operators

The operand must be a bit, std_logic or std_ulogic type of data or an extension of these data types, that is, Bit_vector, Std_logic_vector,std_ulogic_vector.

There are several logical operators for VHDL: ( descending precedence )

ÿnot--Reverse

ÿand--and

ÿor--or

ÿnand--and non-

ÿnor--or non-

ÿxor--XOR

L Arithmetic Operators

Operands can be integers, signed, UNSIGNED, or, if std_logic_signed or std_logic_unsigned are declared, add or subtract data from the Std_logic_vector type.

+--Plus

--Minus