Vpfe register description

Register description:
I. CCDC
1. Synchronization enable register (syncen)
0: vdhden
1: Wen
2. modeset
15: fldstat 0: Odd Field 1: Even Field
14: LPF 3-tap low-pass (anti-aliasing) filter for CCD Data 0: off 1: On
13-12: inpmod input mode 0: CCD raw data 1: YCbCr 16bit 2: YCbCr 8bit
11: pack8 0: normal 16bit to SDRAM 1: pack8 bit to SDRAM
10-8: datasft 0: No shift 1-6: Shift 1-6bit
7: fldmode 0: NON-INTERFACED 1: interfaced (if exwen = 1, it needs to be 0)
6: datapol 0: normal 1: one's conplement
5: exwen 0: Do not use external Wen 1: use external VD/HD as the signal for writing SDRAM
4: fldpol 0: Positive 1: Negative
3: hdpol means the same as above
2: vdpol means the same as above
0: vdhdout 0: VD, HD input 1: VD, HD output
3. Horizontal size register (hsize)
12: adr_updt SDRAM address update mode 0: auto increase 1: auto decrease
11-0: size of the line in lnofst SDRAM. 32 bytes are measured in 16 or 32 pixels.
4. SDRAM line offset register (sdofst)
14: fiinv 0: Non inverse 1: Inverse
13-12: fofst line offset value of odd field (FID = 1) 0-3: + 1-+ 4
11-9: lofst0 line offset values of even line and even field (FID = 0) 0-7: + 1--4
8-6: lofst1 line offset values of odd line and even field (FID = 0) Same as above
5-3: lofst2 line offset values of even line and odd field (FID = 1) Same as above
2-0: lofst3 line offset values of odd line and odd field (FID = 1) Same as above
5. SDRAM address-high register (stadrh)
6. SDRAM address-low register (stadrl)
7. CCD color pattern register (colptn)
8. CCD gain adjustment-r/Ye register (ryegain)
CCD gain adjustment-gr/CY register (grcygain)
CCD gain adjustment-GB/g register (gbggain)
CCD gain adjustment-B/mg register (bmggain)
CCD offset adjustment register (offset)
9. Output clipping value register (outclip)
10. VD interrupt #0 register (vdint0) interrupted set number of rows
11. VD interrupt #1 register (vdint1)
12. Gamma Correction settings register (gammawd)
11-10: mfil1 median filter mode for ipipe 0: No filer 1: Average filer 2: Median filer
9-8: mfil1 Median Filter for SDRAM capture. The value is the same as above.
5: cfap CFA pattern. 0: Mosaic 1: stripe
4-2: gwdi gamma width input (for A-LAW table & H3A port)
0: bits 13-4-3-2-1-0
0: ccdtbl apply gamma (A-LAW) to CCDC data saved to SDRAM 0: Disable 1: Enable
13. rec656 control register (rec656if)
1: eccfh_fvl Error Correction enable 0: Disable 1: Enable
0: r656on rec656 Interface Enable 0: Disable 1: Enable
14. CCD configuration register (ccdcfg)
15: vdlc enable synchronizing function regs on vsync. 0: latched on vsync. 1: No latched
13: msbinvi MSB of chroma input signal stored to SDRAM inverted.0: normal 1: MSB inverted
12: bswd byte swap data stored to SDRAM. 0: normal 1: byte swap
11: y8pos location of Y signal when YCbCr 8bit data is input.0: even pixel 1: Odd Pixel
10: extrg external trigger.0: Diable 1: Enable
9: trgsel signal that initializes SDRAM address when extrg = 1.
0: Wen bit (syncen register). 1: FID input port.
8: wenlog specifies CCD valid area.
0: Internal valid and Wen signals are anded logically.
1: Internal valid and Wen signals are ored logically.
6: fidmd setting of FID detection function.
0: FID signal is latched at the vsync 1: FID signal is not latched.
5: bw656 the data width in rec656 input mode. 0: 8bit 1: 10bit
4: ycinswp y input (Yin [7:0]) and c input (CIN [7:0]) are swapped.
0 :( no_ycin_swap) Yin [7:0] = y signal/CIN [7:0] = C signal.
1 :( ycin_swap) Yin [7:0] = C signal/CIN [7:0] = y signal.
15. Start pixel horizontal register (fmtfe-) for CFA, that is, cmyg to rgbg Conversion
16. number of pixels register (fmtlnh) Same as above
17. Start line vertical register (fmtslv) Same as above
18. number of lines register (fmtlnv) Same as above
19. Lens shading correction configuration 1 register (lsccfg1) Same as above
20. Lens shading correction configuration 2 register (lsccfg2)
21. Lens shading correction-center position (h0) Register (lsch0)
22. Lens shading correction-center position (v0) Register (lscv0)
23. Lens shading correction-horizontal coefficients register (lsckh)
24. Lens shading correction-vertical coefficients register (lsckv)
25. Lens shading correction-memory control register (lscmemctl)
26. Lens shading correction-memory read data register (lscmemq)
27. defect correction-control register (dfcctl)
28. defect correction-vertical saturation level register (dfcvsat)
29. defect correction-memory control register (dfcmemctl)
30. defect correction-set V position register (dfcmem0)
31. defect correction-set h position register (dfcmem1)
32. defect correction-set sub1 register (dfcmem2)
33. defect correction-set sub2 register (dfcmem3)
34. defect correction-set sub3 register (dfcmem4)
35. Color Space converter enable register (cscctl)
36. Color Space converter-coefficients #0 register (cscm0)-(cscm7)
37. Data offset register (dataofst)
15-8 vofst v direction data offset for defect correction and lens shading correction. Range: 0-255.
7-0 hofst H direction data offset for defect correction and lens shading correction. Range: 0-255.
Ii. ipipeif
1. ipipe I/F enable register (enable)
0: Enable SDRAM buffe read start signal and sync signal, only useful in inpsrc (CFG []) = 1, 2 or 3. (CFG)
13-11: datasft SDRAM read data shift (0_6) When inpsrc = 1 or 2. Valid
0 output data (13:0) = read data (15:2)
1 output data () = read data (14)
2 output data (13:0) = read data (13:0 )(
3 output data (13:0) = read data (12:0) & "0"
4 output data (13:0) = read data11: 0) & "00"
5 output data (13:0) = read data (10:0) & "000"
6 Output Data () = read data () & "0000"
2. ipipe I/F configuration register
10: clksel
Ipipeif & ipipe clock select
This register is available when inpsrc = 1 or 3. shocould code "0" When inpsrc = 0 or 2.
0 pixel clock (pclk)
1 divided SDRAM clock as per clkdiv
9: ialaw inverse A-Law Conversion
Applies inverse A-Law (8bit to 10bit) conversion to the SDRAM data.
This register is available when = inpsrc 1 or 2.
0 inverse alaw off
1 inverse alaw on
8: pack8in 8-bit packed mode inpsrc 1 or 2. Valid
0 (normal_16_bits_pixel) 16 bits/Pixel
1 (pack_8_bits_pixel) 8 bits/Pixel
7: avgfilt averaging filter
It applies (1, 2) filter for the RGB/YCbCr data.
0 off
1 On
6-4: clkdiv clock selection when offline mode (SDRAM input? Mode)
Ipipeif/ipipe clock frequency = clkdiv x vpssclk clock frequency (clksel = 1)
0-/2-1/6/8/16/32
3-2: inpsrc CCD/YCbCr data port selection
0 from CCD Controller
1 From SDRAM (raw data)
2 from CCD Controller & SDRAM (darkframe)
3 from SDRAM (YCbCr data)
1: decm pixel decimation
Decimation rate defined by rsz register
0 No decimation
1 decimate
0: oneshot one shot mode
This register is available when inpsrc = 1 or 3.
0 continuous mode
1 One Shot Mode
3. ipipe I/F interval of HD/start pixel in HD register (PPLN)
4. ipipe I/f Number of valid pixels per line register (hnum)
5. ipipe I/f Number of valid lines per frame register (vnum)
6. ipipe I/F memory address (upper) Register (addru)
7. ipipe I/F memory address (lower) Register (addrl)
8. ipipe I/F address offset of each line register (adofs)
9. ipipe I/F horizontal resizing parameter register (rsz) (used when the horizontal pixel is greater than 1344)
6-0 rsz 10 h-70 h the horizontal resizing parameter horizontal resize parameter, 16 to 112, calculated in 16/rsz
10. ipipe I/F gain parameter register (GAIN)
Iii. ipipe
1. ipipe enable register (ipipe_en)
0: in one-shot mode, after processing a frame, en automatically clears 0.
2. One shot mode register (ipipe_mode)
1: WRT cam_wen mode selection. if WRT = 0, each frame is processed regardless of cam_wen. If WRT = 1, it is processed when cam_wen is valid (when ipipeif is generated at that time, it should be set to 0)
0 oneshot one shot mode.
3. Input/output data paths register (ipipe_dpaths)
2 bypass enable raw-Bypass mode through ipipe. When set, the input image width can reach 4096 pixel (only valid when FMt = 1)
0-1 FMT data path through ipipe.
0 (raw2yuv) Bayer input, YCbCr (or RGB) output.
1 (raw2raw) Bayer input, Bayer output.
2 (raw2box) Bayer input, boxcar output.
3 (yuv2yuv) YCbCr (16bit) input, YCbCr (or RGB) Output
4. Color Pattern register (ipipe_colpat)
5. Vertical start position register (ipipe_vst)
6. Vertical processing size register (ipipe_vsz)
7. Horizontal start position register (ipipe_hst)
8. Horizontal processing size register (ipipe_hsz)
9. Arm gated clock control register (gcl_arm)
0 Reg ipipe MMR clock enable.
The on/off Selection of the MMR interface clock which is used for ARM register accesses.
0 off
1 On
10. CCD gated clock control register (gcl_ccd)
2 G2 ipipe G2 clock enable.
The on/off Selection of the clock which is used for the ipipe processing of "CFA" to "422", "histogram ".
0 off
1 On
1 G1 ipipe G1 clock enable.
The on/off Selection of the clock which is used for the ipipe processing of "defect correction" to "whitebalance ".
0 off
1 On
0 G0 ipipe G0 clock enable.
The on/off Selection of the clock which is used for the ipipe processing of "Boxcar ".
0 off
1 On
11. SDR gated clock control register (gcl_sdr) (the clock of the resizer module is active. When the value is 0, it is in the resizer bypass mode)
0 rsz ipipe rsz clock enable.
The on/off Selection of the clock which is used for "resize". The resizer operates in Bypass mode when
This is off.
0 off
1 On
12. Internal table Selection Register (ram_mode)
13. Address Register (ram_adr)
14. Write Data Register (ram_wdt)
15. Read data register (ram_rdt)
16. Interrupt enable register (irq_en)
17. interval of IRQ-2 register (irq_rza)
12-0 Val 0-1fffh interval of irq_2. interrupt signal at every (Val + 1) lines of Resize and RGB output.
18. interval of IRQ-3 register (irq_rzb)
12-0 Val 0-1fffh interval of irq_3. interrupt signal at every (Val + 1) lines of Resize and RGB output
19. defect correction enable register (dfc_en)
20. COPY method selection (from top or from bottom) Register (dfc_sel)
21. Start address in LUT register (dfc_adr)
22. Number of available entries in LUT register (dfc_siz)
23. 2d noise filter enable register (d2f_en)
24. noise filter configuration register (d2f_cfg)
25. Noise Filter LUT values (threshold) Register (d2f_thr [32])
26. Noise Filter LUT values (intensity) Register (d2f_str [32])
27. prefilter enable register (pre_en)
28. prefilter type register (pre_typ)
29. Shift value of adaptive gain register (pre_shf)
30. Constant Gain or adaptive gain slope register (pre_gain)
31. Threshold g register (pre_thr_g)
32. Threshold B register (pre_thr_ B)
33. Threshold 1 register (pre_thr_1)
34. Digital gain register (wb2_dgn)
35. White Balance gain register (wb2_wg_r), (wb2_wg_gr), (wb2_wg_gb) (wb2 _ wg_ B)
36. Matrix coefficient RR register (rgb_mul_rr), rgb_mul_gr, rgb_mul_br), (rgb_mul_rg)
37. Matrix coefficient Gg register (rgb_mul_gg), (rgb_mul_bg), (rgb_mul_rb), (rgb_mul_gb), (rgb_mul_bb)
38. R output offset register (rgb_oft_or), (rgb_oft_og), (rgb_oft_ob)
39. Gamma Correction configuration register (gmm_cfg)
40. Luminance adjustment (contrast and brightness) Register (ycc_adj)
41. matrix coefficient ry register (ycc_mul_ry), (ycc_mul_gy), (ycc_mul_by), (inflow), (inflow), (ycc_mul_rcr), (inflow), (ycc_mul_cea)
42. y output offset register (ycc_oft_y)
43. CB output offset register (ycc_oft_cb)
44. Cr output offset register (ycc_oft_cr)
45. saturation (luminance minimum) Register (ycc_y_min)
46. saturation (luminance maximum) Register (ycc_y_max)
47. saturation (chrominance minimum) Register (ycc_c_min)
48. saturation (chrominance maximum) Register (ycc_c_max)
49. chrominance position (for 422 down Sampler) Register (ycc_phs) (when the input is YCbCr)
50. Edge enhancer enable register (yee_en)
51. mediannr enable register (yee_emf)
52. HPF shift length register (yee_shf)
53. HPF coefficient 00 register (yee_mul_00, 01,02, 22)
54. Fault color suppression enable register (fcs_en)
55. Type Selection of HPF register (fcs_typ)
56. Down shift size (HPF) Register (fcs_shf_y)
57. Down shift size (GAIN) Register (fcs_shf_c)
58. Threshold register (fcs_thr)
59. Intensity register (fcs_sgn)
60. processing mode register (rsz_seq)
4 CRV chroma sampling point change.
0 chroma sampling point is not changed.
1 chroma sampling point is changed from odd-numbered pixels to even-number pixels. The pixel the leftend is removed and the pixel at the right end is duplicated.
3 VRV vertical reversal of output image.
0 processed lines are output in the order of input (normal operation) in vertical direction.
1 The Order of output data is flipped top to bottom.
2 HRV horizontal reversal of output image.
0 processed pixels are output in the order of input (normal operation) in horizontal ction.
1 The Order of output data is flipped left to right.
1 TMM terminal condition of vertical processing.
0 output line number confined mode (normal mode). The module continues output of resized image Untilthe number of output lines reaches the value set by rza_o_vsz and rzb_o_vsz.
1 input line number confined mode. The modules continues output of resized image until the inputnumber of input lines reads the value set by rza_ I _vsz and rzb_ I _vsz. The numbers of output linesare output to tables and tables.
0 seq operation mode of vertical processing.
0 normal mode. The module clears register values and internal buffer values at vsync.
1 continuous mode. resizer holds values from the previous operation. This mode may only be used incombination with input line number confined mode (TMM = 1 ).
61. vertical anti aliasing filter register (rsz_aal)
62. resizer enable register (rsz_en)
63. One shot mode register (rsz_mode)
0 ost one shot mode enable.
0 continuous mode.
1 One shot mode.
64. Vertical start position of the input register (rsz_ I _vst)
11-0 Val 0-fffh vertical start position of image processing.
After ipipe_vst, the Val line is processed as the first line in each image. (calculated after ipipe_vst)
65. vertical size of the input register (rsz_ I _vsz)
11-0 Val 0-fffh number of input lines. This value is used only in input line confined mode. (rsz_seq [TMM] At 0108 H ).
The number of input lines is (Val + 1 ).
66. Horizontal start position of the input register (rsz_ I _hst)
11-0 Val 0-fffh horizontal start position of image processing.
(Rsz_ I _hst [0] is held low so This value must be even). After ipipe_hst, the Val pixel is
Processed as the first pixel.
67. vertical size of the output register (rsz_o_vsz)
11-0 Val 0-fffh vertical size of the output image.
The number of output lines is (Val + 1). (rsz_o_vsz [0] is held high so This value must be odd ).
68. Horizontal start position of the output register (rsz_o_hst)
11-0 Val 0-fffh horizontal position of the first pixel to be output in processed image.
The First val pixels of the resized area in each line are discarded, and the next pixel becomes the first
To be output. (rsz_o_hst [0] is held low so This value must be even ).
69. Horizontal size of the output register (rsz_o_hsz)
11-0 Val 0-fffh horizontal size of output image. The number of pixel in each line is (Val + 1 ).
Rsz [0]: value must be lower than 1344 random t in raw passthu mode.
Rsz [1]: value must be lower than 640. (rsz_o_hsz [0] is held high so This value must be odd ).
70. Initial Phase of vertical resizing process register (rsz_v_phs)
13-0 Val 0-3fffh initial value for the phase value in vertical resizing process. (shocould be set to zero inter t in Frame
Division mode-h). Valid range: 0-8191.
71. Phase of last value in previous resize process register (rsz_v_phs_o)
13-0 Val 0-3fffh phase value of the last line in the previous resizing process. This value is only valid in input line
Number confined mode (rsz_seq [TMM] at 0x0108 ).
72. Vertical resize parameter register (rsz_v_dif)
13-0 Val 0-3fffh vertical resize parameter. The actual resizing ratio is 256/Val.
73. Actual number of output lines register (rsz_v_siz_o)
12-0 Val 0-1fffh Number of actually produced lines in the previous resizing Process
74. Initial Phase of horizontal resizing process register (rsz_h_phs)