What affects the performance of flash memory? Technical Features of nand flash memory

We often say that flash memory is just a general term. To be precise, it is commonly known as non-random access memory (NVRAM). It features that data does not disappear after power failure, therefore, it can be used as external memory. The so-called memory is a volatile memory, which can be divided into two categories: DRAM and SRAM. The memory is usually referred to as dram, that is, the familiar DDR, DDR2, SDR, Edo, etc. Flash memory also has different types, which are mainly divided into two categories: nor type and NAND type.

Classification of flash memory

The nor flash memory differs greatly from the nand flash memory. For example, the nor flash memory is more like memory and has an independent address line and data line, but the price is relatively expensive and the capacity is relatively small; the NAND type is more like a hard disk, and the address line and data line share the I/O line. Similar to the hard disk, all information is transmitted through a hard disk line. In addition, compared with the nor flash memory, the NAND type, the cost is lower, while the capacity is much larger. Therefore, nor flash memory is suitable for frequent random read/write scenarios. It is usually used to store program code and run directly in flash memory. Mobile phones are large users who use nor flash memory, therefore, the "Memory" Capacity of mobile phones is usually not large. nand flash memory is mainly used to store data. Our commonly used FLASH products, such as flash drives and digital storage cards, use nand flash memory.

Here we also need to correct the concept that the flash memory speed is actually very limited, and its operation speed and frequency are much lower than the memory, in addition, the operating efficiency of nand flash memory is much slower than that of memory direct access. Therefore, do not think that the performance bottleneck of the flash drive is the interface, or even take it for granted that the flash drive will achieve a huge performance improvement after using the USB interface.

As mentioned above, the operation efficiency of nand flash memory is low, which is related to its architecture design and interface design, it is indeed like a hard disk (in fact, the compatibility with the hard disk is indeed considered at the beginning of the design of the nand flash memory), its performance is also similar to the hard disk: the operation of small data blocks is very slow, the speed of big data blocks is very fast. This difference is far greater than that of other storage media. This performance feature deserves our attention.

Technical Features of nand flash memory

The basic storage unit of memory and nor flash memory is bit. Users can randomly access any bit information. The basic storage unit of the nand flash memory is page (as you can see, the page of the nand flash memory is similar to the hard disk sector, and one hard disk sector is also 512 bytes ). The effective capacity of each page is a multiple of 512 bytes. The so-called effective capacity refers to the part used for data storage. In fact, we need to add 16 bytes of verification information. Therefore, we can see in the flash manufacturers' technical materials "(512 + 16) byte. At present, the vast majority of nand flash memory with less than 2 GB capacity is (512 + 16) bytes of page capacity. The nand flash memory with more than 2 GB capacity will expand the page capacity to (2048 + 64) bytes.

The nand flash memory is erased in blocks. The Flash write operation must be performed in a blank area. If data already exists in the target area, it must be erased before writing. Therefore, the erasure operation is the basic operation of flash memory. Generally, each block contains 32 512-byte pages with a capacity of 16 KB. When a large-capacity FLASH memory uses 2 kb pages, each block contains 64 pages with a capacity of kb.

Each nand flash memory has eight I/O interfaces. Each data line transmits (512 + 16) bit information each time, and 8 is (512 + 16) x 8 bit, that is, 512 bytes. However, the large-capacity nand flash memory is also increasingly adopting 16 I/O Lines. For example, the Samsung k9k1g16u0a chip is a 64 m x 16 bit NAND FLASH memory with a capacity of 1 GB, the basic data unit is (256 + 8) × 16 bits, or 512 bytes.

During addressing, the nand flash memory transmits 8-bit address information packets through eight I/O interface data lines. Because the size of the flash memory chip is relatively large, a group of eight-bit addresses can only address 256 pages, which is obviously not enough. Therefore, an address transfer usually requires several groups to occupy several clock cycles. The address information of the NAND includes the column address (the start Operation address in the page), block address, and corresponding page address. They are grouped at least three times during transmission and take up three periods. As the capacity increases, there will be more address information and more clock transmission is required. Therefore, an important feature of nand flash memory is that the larger the capacity, the longer the addressing time. Moreover, because the transfer address period is longer than that of other storage media, nand flash memory is less suitable for a large number of small-capacity read/write requests than other storage media.

What are the factors that determine the nand flash memory?

1. Number of pages

As mentioned above, the larger the size of flash memory, the larger the page, the longer the addressing time. However, the extension of this time is not linear, but step-by-step change. For example, a 128 or 512 MB chip needs to transmit address signals in three cycles. a mb or 1 GB chip requires four cycles, while a 2 or 4 GB chip requires five cycles.

2. Page capacity

The size of each page determines the amount of data that can be transferred at a time. Therefore, a large page has better performance. As mentioned above, large-capacity FLASH memory (4 GB) increases the page size from 512 bytes to 2 kb. The increase in page capacity not only increases the capacity, but also improves the transmission performance. Here is an example. Taking Samsung k9k1g08u0m and k9k4g08u0m as examples, the former is 1 GB, 512-byte page capacity, random read (stable) Time is 12 μs, And the write time is 200 μs; the latter is 4 GB, 2 kb page size, random read (stable) Time of 25 μs, write time of 300 μs. Suppose they work at 20 MHz.

Read Performance

The read steps of the nand flash memory are divided into sending commands and addressing information → transferring data to the page register (random read stability time) → data transfer (8 bits per cycle, 512 + 16 or 2 K + 64 requests ).

To read a page, you must:

Five Commands, addressing cycle x 50ns + 12 μs + (512 + 16) x 50ns = 38.7 μs

K9k1g08u0m actual read transmission rate: 512 bytes ÷ 38. 7 μs = 13.2 Mb/s.

To read a page, you must:

Six commands, addressing cycle x 50ns + 25 μs + (2 k + 64) x 50ns = 131.1 μs.

K9k4g08u0m actual read rate: 2 kb bytes limit 131. 1 μs = 15.6 MB/S

Therefore, the use of 2 kb page capacity is also about to increase the read performance by 512 compared with 20% bytes.

Write Performance

The writing steps of the nand flash memory are divided into sending addressing information → transferring data to the page register → sending Command Information → writing data from the Register to the page. The command cycle is also one. We will merge it with the addressing cycle below, but these two parts are not consecutive.

K9k1g08u0m:

Five Commands, addressing cycle x 50ns + (512 + 16) x 50ns + 200 μs = 226.7 μs.

K9k1g08u0m actual write transfer rate: 512 bytes limit 226. 7 μs = 2.2 Mb/s.

K9k4g08u0m:

Six commands, addressing cycle x 50ns + (2 k + 64) x 50ns + 300 μs = 405.9 μs.

K9k4g08u0m actual write rate: 2112 Bytes/405.9 μs = 5 MB/S

Therefore, 2 kb page capacity is used to increase the write performance by more than twice than 512 bytes page capacity.

3. Block capacity

Blocks are the basic unit of the erasure operation. Because each block has almost the same erasure time (the erasure operation usually takes 2 ms, and the time occupied by commands and address information in previous cycles is negligible ), the size of the block directly determines the erasure performance. The page capacity of the large-capacity nand flash memory is increased, and the page size of each block is also increased. Generally, the size of the 4 GB chip is 2 kb × 64 pages = kb, 1 GB core is 512 bytes × 32 pages = 16 kb. It can be seen that, within the same time period, the speed of the former is 8 times that of the latter!

4. I/O Bit Width

In the past, there were eight data lines in the nand flash memory, but 16 data lines emerged from MB. However, due to Controller and other reasons, the x16 chip has relatively few practical applications, but the number will continue to increase in the future. Although the x16 chip still uses a group of 8 bits for transmitting data and address information, the occupation cycle remains unchanged, but the data is transmitted in a group of 16 bits, the bandwidth is doubled. K9k4g16u0m is a typical 64 m × 16 chip. Its page size is still 2 kb, but its structure is (1 K + 32) × 16 bit.

Imitating the above calculation, we can know:

To read a page, you must:

Six commands, addressing cycle x 50ns + 25 μs + (1 K + 32) x 50ns = 78.1 μs.

K9k4g16u0m actual read rate: 2 kb bytes (26.2 μs) = MB/S

K9k4g16u0m:

Six commands, addressing cycle x 50ns + (1 K + 32) x 50ns + 300 μs = 353.1 μs.

K9k4g16u0m actual write transfer rate: 2 kb bytes limit 353. 1 μs = 5.8 MB/S

As you can see, after 16 data lines are added to chips of the same capacity, the read performance is improved by nearly 70%, and the write performance is also improved by 16%.

5. Frequency

The impact of frequency is easy to understand. The operating frequency of nand flash memory is between 20 and 20 ~ 33 MHz, the higher the frequency, the better. Taking k9k4g08u0m as an example, we assume that the frequency is 20 MHz. If we double the frequency to 40 MHz, then k9k4g08u0m needs to read a page:

Six commands, addressing cycle x 25ns + 25 μs + (2 k + 64) x 25ns = 78 μs.

K9k4g08u0m actual read rate: 2 kb bytes limit 78 μs = 26.3 MB/S

As you can see, if the operating frequency of k9k4g08u0m is increased from 20 MHz to 40 MHz, the read performance can be improved by nearly 70%! Of course, the above example is just for convenience of computation. In Samsung's actual product line, k9xxg08uxm can work at a high frequency, rather than k9xxg08u0m. The former can work at 33 MHz at present.

6. Manufacturing Process

The manufacturing process may affect the density of the transistor and the operation time. For example, the write stability and read stability time mentioned above occupy an important part of our computing time, especially when writing data. If the time can be reduced, the performance can be further improved. Can 90nm manufacturing process improve performance? I'm afraid the answer is correct! The actual situation is that as the storage density increases, the required read and write stability time is on the rise. The previous computing example shows this trend. Otherwise, the performance improvement of the 4 GB chip is more obvious.

In summary, although the addressing and operation time of the large-capacity nand flash memory chip will be slightly longer, the effective transfer rate will increase as the page capacity increases, large-capacity chips meet the market demand for capacity, cost, and performance. Increasing data lines and increasing frequency are the most effective way to improve performance. However, commands and address information occupy the operation cycle and some fixed operation time (such as signal stabilization time) such as the impact of technological and physical factors, they will not bring a year-on-year performance improvement.

Samsung k9xxg08xxm flash memory chip architecture

1 page = (2 k + 64) bytes

1 block = (2 k + 64) B × 64pages

= (128 K + 4 K) bytes

1 device = (2 k + 64) B × 64pages × 4096blocks

= 4224 Mbits

Samsung k9xxg08xxm flash memory chip address information

Where: a0 ~ 11 addressing on the page can be understood as "column address ".

A12 ~ 29. Addressing the page can be understood as "line address ".

For convenience, "column addresses" and "Row addresses" are divided into two groups for transmission, instead of directly combining them into a large group. Therefore, each group has several data lines in the last cycle without information transmission. Unused data lines remain low.

The so-called "Row address" and "column address" of nand flash memory are not the definitions we are familiar with in DRAM and SRAM. They are just a relatively convenient expression. For ease of understanding, we can make a vertical section of the preceding three-dimensional nand flash memory chip architecture diagram, it is more intuitive to apply the two-dimensional "rows" and "columns" in this section.