What is decoupling capacitor?

The empirical rule of PCB design: "place a 1 ~ The 10μf Capacitor Filters out low-frequency noise. A 0.01 ~ The capacitance of 0.1 μF is used to filter out high-frequency noise ." Rule of first choice (rule of thumb ). Everyone who works on the circuit knows that some small capacitors need to be placed near the chip. How big is it? How much? How to put it?
Two common simple concepts.
What is bypass? A bypass (bypass) is used to provide a low-impedance path for some harmful parts of the signal. High-frequency interference in the power supply is a typical useless component and needs to be eliminated before entering the target chip. Generally, capacitor is used to achieve this purpose. The capacitor used for this purpose is the so-called bypass capacitor. It utilizes the Frequency Impedance Characteristics of the capacitor (the frequency characteristics of the ideal capacitor decrease with the increase of the frequency ), it can be seen that the bypass capacitor is mainly used for high-frequency interference (high is relative, generally considered as high-frequency interference at or above 20 MHz, and low-frequency ripple at or below 20 MHz ).
What is decoupling? Decouple was first used in multi-level circuits to take measures to ensure signal transmission between the front and back levels without affecting each other's static work points. In the power supply, the decoupling function indicates that when the chip is switched or the output changes, a large current needs to be extracted from the power cord instantaneously. This instantaneous large current may cause the voltage to decrease on the power cord, this causes interference to itself and other devices. To reduce this interference, you need to set up a "small pool" for power storage near the chip to provide this instantaneous large current capability.
In the power supply circuit, both bypass and decoupling are designed to reduce power noise. Bypass is mainly used to reduce the interference of noise on the power supply to the device itself (self-protection); the decoupling is used to reduce the interference of noise generated by the device to the power supply (ugly ). Some people say that the decoupling is for low frequency and bypass for high frequency. I think this is not accurate, and the internal switch operation of the high-speed chip may be as high as GHz, the interference to the power cord is obviously out of the low frequency range. For this purpose, the coupling capacitor also needs to have a good high frequency. In the following discussion, the decoupling and bypass are not intentionally distinguished, so that noise is filtered out regardless of the source of the noise.

After a brief explanation of the bypass and decoupling, let's take a look at how the chip interferes with the power cord. We have established a simple Io buffer model, and the output uses the figure tengzhu I/O drive circuit, an output-level drive consisting of two complementary MOS tubes is a transmission line with the matching resistance of the source end of the string Link (the transmission line impedance is z0 ).

In order to make it a pure document format, try to use text instructions instead of images, which brings some difficulties to understanding, and the readers are smiling. The sum of the package inductance and lead inductance of the power supply pin and ground pin is LV and LG respectively. Two complementary MOS tubes (ground NMOS and PMOS connected to power supply) are used as switches. Assuming that the voltage and current at each point on the transmission line are zero at the initial time, the device will drive the transmission line to a high level at a certain time point, then the device will need to absorb the current from the power supply pin. At the time t1, the PMOS pipe is turned on, and the current flows into the VCC on the PCB. It flows through the encapsulation inductance LV, spanning the PMOS tube, concatenating the terminal resistance, and then flowing into the transmission line, the output current range is VCC/(2 × z0 ). The current continues a full return-trip time on the transmission line network and ends at T2. After that, the entire transmission line is in charge-filled state, and no additional inbound current is needed to maintain it. When the current surges through the encapsulated inductance LV, the voltage will be decreased when the supply points inside the chip are supplied. This disturbance is called synchronous switch noise (SSN, simultaneous switching noise; SSO, simultaneous switching output noise) or Delta I noise in the power supply.
When the PMOS tube is closed at the time t3, this action will not lead to the generation of pulse noise, because the PMOS tube has been in the open state and no current flow. At the same time, enable the NMOS tube. At this time, the transmission line, the ground plane, the encapsulated inductance LG and the NMOS tube form a loop, with instantaneous current flowing through the switch B, in this way, the reference level point is raised at the local node inside the chip. This disturbance is called ground bounce in the power supply system ).
In the actual power supply system, there is a certain Inductance Value for any interconnect lines such as chip pins, PCB cabling, power supply layer, and bottom layer, as a result, the SSN and the ground bullet Noise Used in the above IC-level analysis exist in the same way, not just within the chip. For the entire power distribution system, this is the so-called power supply voltage collapse noise. Because the switch operation of the chip output and the operation inside the chip need to extract a large amount of current from the power supply instantaneously, and the power supply characteristics cannot quickly respond to the current change, the switching frequency of the high-speed switch power supply is only MHz. In order to ensure that the voltage on the power cord near the chip will not be reduced because the SSN and the ground bullet noise will not exceed the limits specified in the device manual, this requires an energy storage capacitor for high-speed current demand near the chip, this is the decoupling capacitor we want.

If the capacitor is an ideal capacitor, the larger the capacitor, the better the choice. Because the larger the capacitor, the more instantaneous power supply capability, the lower the power rail Collapse Value, the more stable the voltage value is. However, the actual capacitor is not an ideal device. Due to the influence of materials and encapsulation, it has additional characteristics such as inductance and resistance; especially in high-frequency environments, it is more like the electrical characteristics of inductance. We all know that the actual capacitance model is simply built with capacitance, resistance, and inductance. In addition to the capacity C of the capacitor, it also includes the following parasitic parameters:
1. equivalent series resistance (resr): The equivalent series resistance of the capacitor is composed of the pin resistance of the capacitor and the equivalent resistance of the two plates of the capacitor. When a large ac current passes through the capacitor, resr consumes energy (resulting in loss) for the capacitor, which is often expressed by the loss factor.
2. equivalent series inductance ESL (lesl): The equivalent series inductance of the capacitor is composed of the pin inductance of the capacitor and the equivalent inductance of the two plates of the capacitor.
3. Equivalent parallel resistance epr rp: This is what we call the capacitor leakage resistance. It is used in AC coupling and storage applications (such as analog integrator and sampling holder) when a capacitor is used in a high-impedance circuit, RP is an important parameter. The charge in an ideal capacitor only changes with the external current. However, the RP in the actual capacitor slows down the charge at the speed determined by the RC time constant.
The two parameters RDA and CDA are also the distribution parameters of the capacitor, but the actual effect should be relatively small, which saves the trouble. Therefore, three important capacitance distribution parameters are available: ESR, ESL, and EPR. The most important of these are the ESR and ESL. In actual analysis of the capacitance model, only the RLC is used to simplify the model, that is, the C, ESR, and ESL of the capacitor are analyzed. Due to the influence of parasitic parameters, especially ESL, the frequency characteristics of the actual capacitor show the impedance and frequency in a "V" curve. When the frequency is low, the capacitance impedance decreases as the frequency increases; when the lowest point is reached, the capacitance impedance is equal to the esr. Later, the impedance increases with the increase of frequency, showing the inductance property (due to ESL ). Therefore, you must consider not only the capacity, but also other factors. Including:
1. capacitance capacity; 2. dielectric material; 3. geometric size and position of the capacitor.

The starting point of all considerations is to reduce the inductance between power sources (to meet the conditions of the maximum power supply capacity), when there is an instantaneous large current flowing through the power supply system, it will not generate large noise to interfere with the power supply pin of the chip. There are two common methods to calculate the required capacitance:
Simple Method: Calculate the size of the required decoupling Capacitor Based on the output-driven changes;
Complex Method: Calculate the size of the coupling capacitor based on the maximum inductance allowed by the power supply system.

Assume that a model has 36 output data lines in a VCC = 3.3v SRAM system. The load of a single data line is cload = 30pf (relatively large ), the output driver needs to drive the load from 0 V to 3.3 V within TR = 2ns (rising time, the required power supply voltage is 3.3 V + 0.3 V/-0.165 v.
We can see that when the output of the SRAM is increased from 0 V to 3 V at the same time, the current extracted from the power supply system is the maximum. At this time, we choose to calculate the required decoupling capacity. We use the first calculation method for calculation. The current size required by a single data line is:
I = cload × (dv/dt) = 30pf × (3 V/2ns) = 45mA;
The current size of the 36 data lines at the same time is itot = 45mA × 36 = 1.62a. The power supply voltage allowed by the chip is reduced to 0.165 v. Suppose we allow the chip to work on the power cord because the noise introduced by SSN is 50mV, then the required capacitance is:
C = I × (Dt/DV) = 1.62a × (2ns/50mV) = 64nf;
Two 34nf capacitors are selected from the standard capacity table for parallel operation to complete this value. As mentioned above, the selection of the decoupling capacitor is not as big as possible, because the larger the capacitor has a larger encapsulation, and the larger encapsulation may introduce a larger ESL, the existence of ESL will cause voltage jitter at the IC pins ), the formula V = L × (DI/dt) indicates that the L of a common SMD capacitor is about 1.5nh, then v = 1.5nh × (1.62a/2ns) = 1.2 V, after considering the equivalent inductance of the entire bypass loop, glitch will be smaller than this value in the actual circuit. Based on some simulation and empirical data done by our predecessors, the glitch on the decoupling capacitor is closely related to the number of bus simultaneously driven.
Because ESL realizes the current supply capability on the power cord at high frequencies, we use the second method to calculate the required decoupling capacity again. In this method, the board is considered from the board level, that is, the capacitance calculation and selection from the perspective of the total inductance of the bypass loop are more practical. Of course, there are more factors to consider, the actual problem is always solved in this way, which requires some compromise and a little compromise.
Using the above assumption, the total inductive strength of the power supply system is the maximum:
Xmax = (dv/di) = 0.05/1.62 = 31m euro;
Here, we need to note that the decoupling capacitor we introduced is to remove noise at a higher frequency than the decoupling capacitor of the power supply, for example, if the serial inductance in circuit board parameters is about lserial = 5nh, the decoupling frequency of the power supply is as follows:
Fbypass = xmax/(2PI × lserial) = 982 kHz, which is the filtering frequency of the power supply. When the frequency is higher than this frequency, the decoupling circuit of the power supply circuit does not work, the chip coupling capacitor needs to be introduced for filtering. Another parameter-the Turning Point frequency fknee is introduced, which determines the main energy distribution in the digital circuit. The component above this frequency does not contribute to the change of the rising and falling edges of the digital circuit. This issue is discussed in detail in the first chapter of the high-speed digital design: A Hand Book of black magic. The formula is introduced as follows:
Fknee = (1/2 × TR) = 250 MHz, where TR = 2ns;
It can be seen that fknee is far greater than fbypass, and the serial inductance of 5nh is definitely not good. Computing:
Ltot = xmax/(2PI × fknee) = (xmax × TR/PI) = 19.7ph;
As mentioned above, the serial inductance of the common SMD capacitor is around 1.5nh, and the number of capacitors required is:
N = (lserial/ltot) = 76. In addition, when the frequency drops to fbypass, it should also meet the board-level anti-DDoS requirements:
Carray = (1/(2PI × fbypass × xmax) = 5.23 UF;
Celement = carray/N = 69nf;
Wow, it's really not a small number. It's so much! If there are other devices acting simultaneously on the board, more capacitors are needed! If it cannot be deprecated, you can only select other capacitors with smaller inductance values.

The MLCC capacitors are used for decoupling. The common MLCC capacitors can be divided into the first type of NPO media because of different media, the second and third types of media, such as X7R and z5v. The EIA uses three letters for the second and third types of media and classifies them according to the relationship between the capacitance value and the temperature as follows:
The first number indicates the temperature of the lower limit category:
X:-55 degrees; Y:-30 degrees; Z: + 10 degrees
The second number indicates the maximum temperature:
4: + 65 degrees; 5: + 85 degrees;
The third digit indicates a capacity error of 25 degrees:
P: + 10%/-10%; R: + 15%/-15%; s: + 22%/-22%;
T: + 22%/-33%; U: + 22%/-56%; V: + 22%/-82%
For example, the common z5v, indicating that the operating temperature is 10 degrees ~ 85 degrees, nominal capacity deviation + 22%/-82%, we are still using this.

The capacity of the capacitor with good media performance is not large, and the medium constant with large capacity is not good. Why are you always so contradictory! It is particularly important that the capacitance value provided by the MLCC capacitor refers to the electrostatic capacity, which indicates the capacitance measured at a very low voltage, when the DC voltage at both ends of the capacitor increases at a voltage not greater than the voltage of the capacitor, the electrical capacity will decrease sharply. For example, in the test data of a MLCC capacitor with a voltage of 16 V, there are:
0 V --> 100%, 8 V --> 86%, 12 V --> 68%, 16v--55%.
I did not pay attention to this feature and had a painful lesson in a circuit design.

The last reference to the capacitor placement is the old saying: "The rule of thumb is to place the capacitor as close as possible to the IC