What is in the first function systeminit ()?

The systeminit () function appears in the first line of the main () function. We can see its importance. Previously, the systeminit () function has never been concerned, but only knows that it is a function for initializing the stm32 system. Today, I decided to take a closer look and start learning stm32 again. This function is in system_stm32f10x.c. The C file is mainly used for hardware configuration.

/** @addtogroup STM32F10x_System_Private_Functions  * @{  *//**  * @brief  Setup the microcontroller system  *         Initialize the Embedded Flash Interface, the PLL and update the   *         SystemCoreClock variable.  * @note   This function should be used only after reset.  * @param  None  * @retval None  */void SystemInit (void){  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */  /* Set HSION bit */  RCC->CR |= (uint32_t)0x00000001;  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */#ifndef STM32F10X_CL  RCC->CFGR &= (uint32_t)0xF8FF0000;#else  RCC->CFGR &= (uint32_t)0xF0FF0000;#endif /* STM32F10X_CL */       /* Reset HSEON, CSSON and PLLON bits */  RCC->CR &= (uint32_t)0xFEF6FFFF;  /* Reset HSEBYP bit */  RCC->CR &= (uint32_t)0xFFFBFFFF;  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */  RCC->CFGR &= (uint32_t)0xFF80FFFF;#ifdef STM32F10X_CL  /* Reset PLL2ON and PLL3ON bits */  RCC->CR &= (uint32_t)0xEBFFFFFF;  /* Disable all interrupts and clear pending bits  */  RCC->CIR = 0x00FF0000;  /* Reset CFGR2 register */  RCC->CFGR2 = 0x00000000;#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)  /* Disable all interrupts and clear pending bits  */  RCC->CIR = 0x009F0000;  /* Reset CFGR2 register */  RCC->CFGR2 = 0x00000000;      #else  /* Disable all interrupts and clear pending bits  */  RCC->CIR = 0x009F0000;#endif /* STM32F10X_CL */    #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)  #ifdef DATA_IN_ExtSRAM    SystemInit_ExtMemCtl();   #endif /* DATA_IN_ExtSRAM */#endif   /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */  /* Configure the Flash Latency cycles and enable prefetch buffer */  SetSysClock();#ifdef VECT_TAB_SRAM  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */#else  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */#endif }

From the function description, this function isInitialize the internal falsh, PLL, and update the system clock.. This function must be called After resetting and starting.

RCC->CR |= (uint32_t)0x00000001;

First line of codeOperate the clock control register to enable the internal 8 m high-speed clock, From here we can see thatAfter the system is started, it first depends on the internal clock source..

#ifndef STM32F10X_CL  RCC->CFGR &= (uint32_t)0xF8FF0000;#else  RCC->CFGR &= (uint32_t)0xF0FF0000;

The two lines of code areOperation clock configuration register. It mainly sets the MCO (microcontroller clock output) PLL correlation (PLL multiplier coefficient, PLL input clock source), adcpre (ADC clock), ppre2 (high-speed APB frequency division coefficient ), ppre1 (low-speed APB division coefficient), hpre (AHB pre-division coefficient), SW (system clock switching ),At the beginning, the system clock is switched to Hsi, which serves as the initial clock of the system.. Macro stm32f10x_cl is a macro related to a specific stm32 chip.

  /* Reset HSEON, CSSON and PLLON bits */  RCC->CR &= (uint32_t)0xFEF6FFFF;  /* Reset HSEBYP bit */  RCC->CR &= (uint32_t)0xFFFBFFFF;  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */  RCC->CFGR &= (uint32_t)0xFF80FFFF;

Which of the following statements is:Configure relevant parameters when HSE, CSS, and PLL are disabled, and then enable them to take effect..

#ifdef STM32F10X_CL  /* Reset PLL2ON and PLL3ON bits */  RCC->CR &= (uint32_t)0xEBFFFFFF;  /* Disable all interrupts and clear pending bits  */  RCC->CIR = 0x00FF0000;  /* Reset CFGR2 register */  RCC->CFGR2 = 0x00000000;#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)  /* Disable all interrupts and clear pending bits  */  RCC->CIR = 0x009F0000;  /* Reset CFGR2 register */  RCC->CFGR2 = 0x00000000;      #else  /* Disable all interrupts and clear pending bits  */  RCC->CIR = 0x009F0000;#endif /* STM32F10X_CL */

This section mainly refersRelated to interrupt settings. At the beginning, we needDisable all interruptions and clear all interrupt flags. Different hardware is different.

#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)  #ifdef DATA_IN_ExtSRAM    SystemInit_ExtMemCtl();   #endif /* DATA_IN_ExtSRAM */#endif

This sectionSet external RamThe stm32f103rbt I used has nothing to do with it.

SetSysClock();

This is another function, mainlyConfigure the system clock frequency. The Division values of hclk, pclk2, and pclk1 represent AHB, apb2, and apb1 respectively. Of course, I did other things,Configure flash latency period and enable prefetch buffer period. The configuration below is not detailed yet.

#ifdef VECT_TAB_SRAM  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */#else  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */#endif 

This code mainly implementsOrientation table relocation. Based on whether you want to locate the vector table in internal SRAM or internal flash. This SCB was not found in the stm32 reference manual since it was related to the Cortex-M3 kernel. So st did not include it. We will learn about the kernel later. Here we will remind ourselves.

Then let's see what the setclock () function in systeminit () has done.

static void SetSysClock(void){#ifdef SYSCLK_FREQ_HSE  SetSysClockToHSE();#elif defined SYSCLK_FREQ_24MHz  SetSysClockTo24();#elif defined SYSCLK_FREQ_36MHz  SetSysClockTo36();#elif defined SYSCLK_FREQ_48MHz  SetSysClockTo48();#elif defined SYSCLK_FREQ_56MHz  SetSysClockTo56();  #elif defined SYSCLK_FREQ_72MHz  SetSysClockTo72();#endif  /* If none of the define above is enabled, the HSI is used as System clock    source (default after reset) */ }

It can be seen thatSet different system clocks based on different macros. These macros are in the same source file as the function.. The official website is very considerate. We only need to select the corresponding macro to quickly configure the system clock.

#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)/* #define SYSCLK_FREQ_HSE    HSE_VALUE */ #define SYSCLK_FREQ_24MHz  24000000#else/* #define SYSCLK_FREQ_HSE    HSE_VALUE *//* #define SYSCLK_FREQ_24MHz  24000000 */ /* #define SYSCLK_FREQ_36MHz  36000000 *//* #define SYSCLK_FREQ_48MHz  48000000 *//* #define SYSCLK_FREQ_56MHz  56000000 */#define SYSCLK_FREQ_72MHz  72000000#endif

For example, here I needTo configure the system clock to 72 MHz, you only need to remove the annotator on both sides of # define sysclk_freq_72mhz 72000000.

This function contains the setsysclockto72 () function, which is configured in the specific operation register.

#elif defined SYSCLK_FREQ_72MHz/**  * @brief  Sets System clock frequency to 72MHz and configure HCLK, PCLK2   *         and PCLK1 prescalers.   * @note   This function should be used only after reset.  * @param  None  * @retval None  */static void SetSysClockTo72(void){  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;    /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/      /* Enable HSE */      RCC->CR |= ((uint32_t)RCC_CR_HSEON);   /* Wait till HSE is ready and if Time out is reached exit */  do  {    HSEStatus = RCC->CR & RCC_CR_HSERDY;    StartUpCounter++;    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));  if ((RCC->CR & RCC_CR_HSERDY) != RESET)  {    HSEStatus = (uint32_t)0x01;  }  else  {    HSEStatus = (uint32_t)0x00;  }    if (HSEStatus == (uint32_t)0x01)  {    /* Enable Prefetch Buffer */    FLASH->ACR |= FLASH_ACR_PRFTBE;    /* Flash 2 wait state */    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;         /* HCLK = SYSCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;          /* PCLK2 = HCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;        /* PCLK1 = HCLK */    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;#ifdef STM32F10X_CL    /* Configure PLLs ------------------------------------------------------*/    /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */    /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */            RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |                             RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);      /* Enable PLL2 */    RCC->CR |= RCC_CR_PLL2ON;    /* Wait till PLL2 is ready */    while((RCC->CR & RCC_CR_PLL2RDY) == 0)    {    }           /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */     RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |                             RCC_CFGR_PLLMULL9); #else        /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |                                        RCC_CFGR_PLLMULL));    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);#endif /* STM32F10X_CL */    /* Enable PLL */    RCC->CR |= RCC_CR_PLLON;    /* Wait till PLL is ready */    while((RCC->CR & RCC_CR_PLLRDY) == 0)    {    }        /* Select PLL as system clock source */    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;        /* Wait till PLL is used as system clock source */    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)    {    }  }  else  { /* If HSE fails to start-up, the application will have wrong clock          configuration. User can add here some code to deal with this error */  }}#endif

The above code needs to be carefully read. This is almost the case for systeminit.