What is the memory latency

Memory latency is the delay that is caused by waiting for access to stored data in the system's memory to complete. The fundamental problem is that the processor (such as the intel® xeon® processor) has a frequency of nearly 4 GHz, while the memory chip rate is only a MHz (such as DDR 3200 memory)-The clock speed ratio is 10:1. Therefore, when the processor needs data items that are outside the memory cache, each cycle must wait 10 cycles for the memory chip to complete the extraction and delivery of the data. Typically, these extracts need to retrieve multiple memory cycles, and then take longer to pass through the path to the processor. This means that extracting data consumes hundreds of processor clock cycles, during which the application cannot handle any other tasks.

Memory latency indicates when the system waits for a memory response before it enters the ready state of the data access operation, which is usually represented by 4 consecutive Arabic numerals, such as "3-4-4-8", which, in general, is larger in four numbers, and the smaller the 4 digits, the better memory performance. Because there is no lower latency than 2-2-2-5, the international Memory Standards Organization believes that the 0 or 1 latency cannot be achieved with today's dynamic memory technology. But it's not that the smaller the latency the higher the memory performance, because the Cl-trp-trcd-tras four values are used in conjunction, the degree of interaction is very large, and also is not the largest value of its performance is the worst, then more reasonable matching parameters are important.

The first number is most important, indicating the delay between registering the Read command to the first output data (CAS latency), which is the CL value, and the unit is the clock cycle. This is the response time of the longitudinal address pulse.

The second number represents the memory line address controller pre-charging time (RAS precharge), or TRP. Refers to the amount of memory that is accessed from the end of a row to the beginning of a restart.

The third number represents the delay time from the memory row address to the column address (RAS to CAS Delay), or TRCD.

The fourth digit indicates the memory row address controller activation time Act-to-precharge precharge Delay (TRAS).

When you choose to purchase memory, it is best to choose the same CL set of memory, because different speed of memory mixed in the system, the system will run at a slower speed, that is, when CL2.5 and CL2 memory plug in the host, the system will automatically let two of the memory are working in the CL2.5 state, resulting in waste of resources.