Why the setup and hold in TLF can be negative

Summarize:

Simply put, because the flip-flop port to the gate has a delay, if the clock that paragraph delay is significantly larger, the setup may be negative, if the flip-flop port Gata that period of delay is significantly too large, hold may take a negative value. In my opinion, both of them are used to fine tune the same asynchronous problem when the data and clock pass through the filp-flop, so that the data and clock can not be changed so that the flip-flop transmission signal is not passed through.

As shown below edge-triggered (rise) D flip-flop, in the case of a single flip-flop, the settling time Tsu generally corresponds to the G1 and G2 and non-gate delays, while the retention time thold generally corresponds to G3 and G4 delays. In Figure 1, CLK from 0 to 1,d from D1 to D2, a TSU must be advanced to convert the G1/G2 output to D2. In Figure 2, CLK keeps 1,d from D2 to D3, and a thold must be postponed to make the G3/G4 output already D2. The corresponding timing library in the setup and hold time should refer to, 1, CLK to G3/G4 delay is too large, in order to ensure that the data can be "on time" to reach the G3/G4 input to make signal d normal input, so setup time to take a negative value; 2,d to G2 delay too large, d to g1/g2 and non-gate delay too large, may affect the data transmission rate and other factors, then hold negative.

1. Edge D trigger (rising edge) and its setup time and hold time principle

When clk=0, with the output of the non-gate G3 and G4 are 1, the output of 1 feedback to G1 and G2 as input, resulting in G1 and G2 output is D and D, the output of D and D are also feedback to G3 and G4, while G5 and G6 have been locked in the previous data, not affected by the input.

2, when clk=1, with non-gate G3 and G4 output into/d and D, output to G5 and G6 as input, according to the principle of latch, G5 and G6 will eventually stable output Q and q

Then consider the delay with the non-gate.

The delay of G2 and G1 is set to T1, when clk=0, if d before the clock jumps (t< T1) time is updated from D1 to D2, then G1 and G2 output values at clock-hopping time are definitely D1 and/d1, not D2 and/D2, which in turn affect G3 and G4 output. If the output of G1 and G2 is to be D2 and/D2, then D must be required to maintain the T1 stability in the D2 time before the clock jumps. this T1 is to set the time Tsu. This can be understood.

When Clk=1, the delay ofG3 and G4 is T2when clk=1, if D is updated from T<t2 to D2 after the clock-hopping T (D3) Time, Since the inputs of the G3 and G4 remain at 1 for the time of T, the update of D affects the output of the G2 and G1, which in turn affects the output of G3 and G4, thus affecting the output of G5 and G6, causing the output Q and q to oscillate or metastable. T2 to keep the time Thold.

The principle of negative 2.Setup and hold

From the above principle can be seen:Tsu and thold can not be negative . TLF in the file Setup time and the Hold Time The reference time period of a synchronous transmission timing circuit should be taken to enable the data path and clock path to traverse Flip-flop There is no asynchronous phenomenon which results in the oscillation or metastable state of the data transmission.

In Figure 1, CLK from 0 to 1,d from D1 to D2, a TSU must be advanced to convert the G1/G2 output to D2. In Figure 2, CLK keeps 1,d from D2 to D3, and a thold must be postponed to make the G3/G4 output already D2. The corresponding timing library in the setup and hold time should refer to, 1, CLK to G3/G4 delay is too large, in order to ensure that the data can be "on time" to reach the G3/G4 input to make signal d normal input, so setup time to take a negative value; 2,d to G2 delay too large, d to g1/g2 and non-gate delay too large, may affect the data transmission rate and other factors, then hold negative.

Why the setup and hold in TLF can be negative