Working serial communication

Header File//

Module My_uart_top (
Clk,rst_n,rs232_rx,rd_fifo_ena,rd_fifo_data,
Rs232_tx,wr_fifo_req,rd_fifo_req,wr_fifo_data,clk_bps_tx,clk_h
);

Inputs
Input clk;//50MHz?????
Input rst_n;//?????? Lambda???
Input rs232_rx;//RS232???????????
Input Rd_fifo_ena;
input [7:0] rd_fifo_data;

Outputs
Output rs232_tx;//rs232???????????
Output wr_fifo_req;
Output rd_fifo_req;
Output [7:0] wr_fifo_data;
Output CLK_BPS_TX;
Output clk_h;

Wire Clk_bps_rx;
Wire Clk_bps_tx;
Wire Bps_start_rx;
Wire Bps_start_tx;
Wire rd_fifo_ena1;
Wire [7:0] rd_fifo_data1;//??????????????????????????????
Wire [7:0] CNT;

Wire rd_fifo_0 = (cnt>=6)? Rd_fifo_req:1 ' B0;
Wire Clk_100mhz;

/////////////////////////////////////////////////////////////////////////////////////////
------RX---------//
//
PLLPLL (
. Inclk0 (CLK),
. C0 (CLK),
. C1 (clk_25m)

);

Speed_selectspeed_rx (. CLK (CLK),//??????????? 飬?????????? 鸴? Ã?????????????
. Rst_n (Rst_n),
. Bps_start (BPS_START_RX),
. clk_bps (CLK_BPS_RX)
);

My_uart_rxuart_rx (. CLK (CLK),//???????????
. Rst_n (Rst_n),
. RS232_RX (RS232_RX),
. clk_bps (CLK_BPS_RX),
. Clk_h (Clk_h),

. en_1 (En_1),


. Bps_start (BPS_START_RX),
. Wr_fifo_data (Wr_fifo_data),
. Wr_fifo_req (Wr_fifo_req)//"1"
);

Wr_fifo FIFO (
. Clock (CLK),
. Data (Wr_fifo_data),
. Rdreq (Rd_fifo),
. Wrreq (Wr_fifo_req),
. Empty (RD_FIFO_ENA1),
. Full (),
. Q (RD_FIFO_DATA1),
. USEDW (CNT)
//);

//////////////////////////////////////////////////////////////////////////////////////////
//
Speed_selectspeed_tx (. CLK (CLK),//??????????? 飬?????????? 鸴? Ã?????????????
. Rst_n (Rst_n),
. Bps_start (BPS_START_TX),
. clk_bps (CLK_BPS_TX)
);

WIRE[7:0] Wr_fifo_data;
Wire en_1;

My_uart_txuart_tx (. CLK (CLK),//???????????
. Rst_n (Rst_n),
. clk_bps (CLK_BPS_TX),
. Rd_fifo_data (Rd_fifo_data),
. Rd_fifo_ena (Rd_fifo_ena),

. Wr_fifo_data (Wr_fifo_data),
. en_1 (En_1),


. RS232_TX (RS232_TX),
. Bps_start (BPS_START_TX),
. Rd_fifo_req (Rd_fifo_req)
);

Wire rd_fifo_req;
Zh_1 zh_1 (
. CLK (CLK),
. Rd_fifo_req (Rd_fifo_req),
. Wrfifo_1 (Wr_fifo_data)
//. Chu_1 (chu_1)

);

Zh_2zh_2 (
. CLK (CLK),
. Wrfifo_1 (Wr_fifo_data),
. Rd_fifo_req (Rd_fifo_req),
. clk_25m (clk_25m)
);



Endmodule

Speed Selection//
Module Speed_select (clk,rst_n,bps_start,clk_bps);

Input Clk;//50mhz?????
Input rst_n;//?????? Lambda???
Input bps_start;//???????????????????????????? Lambda
Output clk_bps;//clk_bps???????????????????? Lambda??? м???????

Parameter BPS9600 = 5207,//??????? 9600bps
BPS19200 = 2603,//??????? 19200bps
BPS38400 = 2603,//??????? 38400bps BPS38400 = 1301,
BPS57600 = 867,//??????? 57600bps
bps115200= 433;//??????? 115200bps

Parameter bps9600_2 = 2603,
Bps19200_2= 1301,
Bps38400_2= 1301,//650
Bps57600_2= 433,
Bps115200_2 = 216;

parameterclk_100m = 1000000,
BTF9600 = 96,
BTF19200 = 192,
BTF38400 = 384,
BTF57600 = 576,
BTF115200 = 1152;

REG[12:0] bps_para;//????????????
REG[12:0] bps_para_2;//????????????
REG[12:0] cnt;//???????
Reg clk_bps_r;//?????????????

Reg[31:0]clk_count;

//----------------------------------------------------------
REG[2:0] uart_ctrl;//UART??????????????
//----------------------------------------------------------

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Uart_ctrl <= 3 ' d2;//????????? 38400bps
Else
Case (Uart_ctrl)//??????????
3 ' D0:begin
Bps_para <= BPS9600;
bps_para_2 <= bps9600_2;
End
3 ' D1:begin
Bps_para <= BPS19200;
bps_para_2 <= bps19200_2;
End
3 ' D2:begin
Bps_para <= BPS38400;
bps_para_2 <= bps38400_2;
End
3 ' D3:begin
Bps_para <= BPS57600;
bps_para_2 <= bps57600_2;
End
3 ' D4:begin
Bps_para <= BPS115200;
bps_para_2 <= bps115200_2;
End
Default:;
Endcase
End

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
CNT <= "D0;
else if (Bps_start)
if (Cnt==bps_para)
CNT <= "D0;
Else
CNT <= cnt + 1 ' b1;//????????????????
Else
CNT <= "D0;
End

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Clk_bps_r <= 1 ' b0;
else if (cnt==bps_para_2)//&& Bps_start)
Clk_bps_r <= 1 ' b1;//clk_bps_r??????????????????? Lambda??? м???????
Else
Clk_bps_r <= 1 ' b0;
End

Assign clk_bps = Clk_bps_r;

Endmodule

/*

Input Clk;//50mhz?????
Input rst_n;//?????? Lambda???
Input bps_start;//???????????????????????????? Lambda
Output clk_bps;//clk_bps???????????????????? Lambda??? м???????

Parameter BPS9600 = 5207,//??????? 9600bps
BPS19200 = 2603,//??????? 19200bps
BPS38400 = 2603,//??????? 38400bps BPS38400 = 1301,
BPS57600 = 867,//??????? 57600bps
bps115200= 433;//??????? 115200bps

Parameter bps9600_2 = 2603,
Bps19200_2= 1301,
Bps38400_2= 1301,//650
Bps57600_2= 433,
Bps115200_2 = 216;

parameterclk_100m = 1000000,
BTF9600 = 96,
BTF19200 = 192,
BTF38400 = 384,
BTF57600 = 576,
BTF115200 = 1152;

REG[12:0] bps_para;//????????????
REG[12:0] bps_para_2;//????????????
REG[12:0] cnt;//???????
Reg clk_bps_r;//?????????????

Reg[31:0]clk_count;

//----------------------------------------------------------
REG[2:0] uart_ctrl;//UART??????????????
//----------------------------------------------------------

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Uart_ctrl <= 3 ' d2;//????????? 38400bps
Else
Case (Uart_ctrl)//??????????
3 ' D0:begin
Bps_para <= BPS9600;
bps_para_2 <= bps9600_2;
End
3 ' D1:begin
Bps_para <= BPS19200;
bps_para_2 <= bps19200_2;
End
3 ' D2:begin
Bps_para <= BPS38400;
bps_para_2 <= bps38400_2;
End
3 ' D3:begin
Bps_para <= BPS57600;
bps_para_2 <= bps57600_2;
End
3 ' D4:begin
Bps_para <= BPS115200;
bps_para_2 <= bps115200_2;
End
Default:;
Endcase
End

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
CNT <= "D0;
else if (Bps_start)
if (Cnt==bps_para)
CNT <= "D0;
Else
CNT <= cnt + 1 ' b1;//????????????????
Else
CNT <= "D0;
End

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Uart_ctrl <= 3 ' d4;//????????? 38400bps
Else
Case (Uart_ctrl)//??????????
3 ' d0:begin
Bps_para <= BTF9600;
End
3 ' d1:begin
Bps_para <= BTF19200;
End
3 ' d2:begin
Bps_para <= BTF38400;
End
3 ' d3:begin
Bps_para <= BTF57600;
End
3 ' d4:begin
Bps_para <= BTF115200;
End
Default:;
Endcase
End

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Clk_count <= "D0;
else if (Bps_start)
if (Clk_count >= clk_100m)
Begin
Clk_count <= clk_count-clk_100m + Bps_para;
Clk_bps_r <= 1 ' b0;
End
else if (Clk_count >= CLK_100M/2)
Begin
Clk_bps_r <= 1 ' b1;//clk_bps_r??????????????????? Lambda??? м???????
Clk_count <= Clk_count + Bps_para;
End
Else
Begin
Clk_count <= Clk_count + bps_para;//????????????????
Clk_bps_r <= 1 ' b0;
End
Else
Clk_count <= "D0;
End

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Clk_bps_r <= 1 ' b0;
else if (clk_count >= CLK_100M/2)//&& Bps_start)
Clk_bps_r <= 1 ' b1;//clk_bps_r??????????????????? Lambda??? м???????
Else
Clk_bps_r <= 1 ' b0;
End

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
CNT <= "D0;
else if ((Cnt==bps_para) | | | (~bps_start))
CNT <= "D0;
Else
CNT <= cnt + 1 ' b1;//????????????????
End

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Clk_bps_r <= 1 ' b0;
else if (cnt==bps_para_2)//&& Bps_start)
Clk_bps_r <= 1 ' b1;//clk_bps_r??????????????????? Lambda??? м???????
Else
Clk_bps_r <= 1 ' b0;
End

Assign clk_bps = Clk_bps_r;

Endmodule

*/

Send Data//

Module MY_UART_RX (clk,rst_n,rs232_rx,clk_bps,bps_start,wr_fifo_data,wr_fifo_req,en_1,clk_h);

Input CLK;
Input rst_n;
Input RS232_RX;
Input clk_bps;

Output en_1;
Output Reg Clk_h;

Output Bps_start;
Output [7:0] wr_fifo_data;
Output wr_fifo_req;

Reg[31:0]cnt1;
Parameter sec_time=100;
[Email protected] (Posedge CLK)
if (cnt1 = = sec_time)
Begin
Cnt1 <= "B0;
Clk_h =!clk_h;
End
else cnt1 <= cnt1 + 1 ' B1;

Reg CLK_BPS_REG0;
Reg CLK_BPS_REG1;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
Clk_bps_reg0 <= 1 ' b0;
CLK_BPS_REG1 <= 1 ' b0;
End
Else
Begin
Clk_bps_reg0 <= clk_bps;
CLK_BPS_REG1 <= clk_bps_reg0;
End
End

Reg RS232_RX_REG0,RS232_RX_REG1;
Wire Neg_rs232_rx;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
Rs232_rx_reg0 <= 1 ' b0;
RS232_RX_REG1 <= 1 ' b0;
End
Else
Begin

en_1<=bps_start;





Rs232_rx_reg0 <= Rs232_rx;
RS232_RX_REG1 <= rs232_rx_reg0;
End
End

Assign Neg_rs232_rx = Rs232_rx_reg1 && ~rs232_rx_reg0;

Reg Bps_start;
Reg Wr_fifo_req;
Regrx_int;
reg [3:0]num;
Regrs232_start;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
En_1<=1 ' B0;

Rx_int <= 1 ' b0;
Bps_start <= 1 ' b0;
Wr_fifo_req <= 1 ' b0;
En_1<=1 ' B0;

Rs232_start <= 1 ' B1;
Rs232_start <= 1 ' b0;
End
else if ((Neg_rs232_rx = = 1 ' B1) && (Rs232_start = = 1 ' b0))//once per send
Begin

Rx_int <= 1 ' B1;
Bps_start <= 1 ' B1;
Wr_fifo_req <= 1 ' b0;
End
else if (num==4 ' D10)
Begin
Rs232_start <= 1 ' b0;
Rx_int <= 1 ' b0;
Bps_start <= 1 ' b0;
Wr_fifo_req <= 1 ' B1;

En_1<=1 ' B1;

End
Else
Begin
Rx_int <= Rx_int;
Bps_start <= Bps_start;
Wr_fifo_req <= 1 ' b0;

En_1<=1 ' B0;

End
End

reg [7:0] rx_data_r;
reg [9:0] rx_temp_data;
reg [10:0] CNT;
Reg En_1;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin

En_1<=1 ' B0;
Rx_temp_data <= 8 ' D0;
Num <= 4 ' D0;
Rx_data_r <= 8 ' D0;
End
else if (rx_int)
begin//???????????
if (clk_bps = = 1 ' B1) && (clk_bps_reg0 = = 1 ' b0))//Detect his rising edge
begin//?????????????,??????????????? Lambda?? 8bit???????????? Lambda
Num <= num + 1 ' b1;


Case (NUM)
4 ' d0:rx_temp_data[0] <= rs232_rx;//??? Lambda
4 ' d1:rx_temp_data[1] <= rs232_rx;//0 bit
4 ' d2:rx_temp_data[2] <= rs232_rx;//1 bit
4 ' d3:rx_temp_data[3] <= RS232_RX;//2 bit
4 ' d4:rx_temp_data[4] <= RS232_RX;//3 bit
4 ' d5:rx_temp_data[5] <= RS232_RX;//4 bit
4 ' d6:rx_temp_data[6] <= RS232_RX;//5 bit
4 ' d7:rx_temp_data[7] <= RS232_RX;//6 bit
4 ' d8:rx_temp_data[8] <= RS232_RX;//7 bit
4 ' d9:rx_temp_data[9] <= rs232_rx;//???? Lambda
Default:;
Endcase
End
else if (num==4 ' D10)
Begin


En_1<=1 ' B1;

Num <= 4 ' D0;
//????? stopλ??????, num????
Rx_data_r <= rx_temp_data[8:1];//????????? 浽???????? Rx_data??
End
else En_1<=1 ' B0;

End
End

Assign wr_fifo_data = Rx_data_r;

Endmodule

Data collection//

Module MY_UART_TX (clk,rst_n,clk_bps,rd_fifo_data,rd_fifo_ena,rs232_tx,bps_start,rd_fifo_req,wr_fifo_data,en_1);

Input CLK;
Input rst_n;
Input clk_bps;
input [7:0] rd_fifo_data;
Input Rd_fifo_ena;
input [7:0] wr_fifo_data;
Input en_1;

Output RS232_TX;
Output Bps_start;
Output rd_fifo_req;

Reg CLK_BPS_REG0;
Reg CLK_BPS_REG1;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
Clk_bps_reg0 <= 1 ' b0;
CLK_BPS_REG1 <= 1 ' b0;
End
Else
Begin
Clk_bps_reg0 <= clk_bps;
CLK_BPS_REG1 <= clk_bps_reg0;
End
End

Reg RD_FIFO_ENA_REG0;
Reg RD_FIFO_ENA_REG1;
Wire Neg_rd_fifo_ena;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
Begin
Rd_fifo_ena_reg0 <= 1 ' b0;
RD_FIFO_ENA_REG1 <= 1 ' b0;
End
Else
Begin
Rd_fifo_ena_reg0 <= Rd_fifo_ena;
RD_FIFO_ENA_REG1 <= rd_fifo_ena_reg0;
End
End

Assign Neg_rd_fifo_ena = RD_FIFO_ENA_REG1 & ~rd_fifo_ena_reg0;

Reg Rd_fifo_req;
Reg Bps_start;
Reg Tx_en;
REG[3:0] num;
REG[7:0] Tx_data;

reg [3:0] state;

Always @ (Posedge CLK or Negedge rst_n)
Begin

if (!rst_n)
Begin
Bps_start <= 1 ' b0;
Tx_en <= 1 ' b0;
Tx_data <= 8 ' D0;

Rd_fifo_req <= 1 ' b0;
State <= 4 ' b0001;
End
Else
Case (state)

Changes
4 ' b0001://if (rd_fifo_ena_reg1==1 ' B0)
if (en_1)
Begin
State <= 4 ' b0010;
Rd_fifo_req <= 1 ' B1;
Bps_start <= 1 ' B1;
Tx_en <= 1 ' B1;
End
Else
Begin
State <= 4 ' b0001;
Rd_fifo_req <= 1 ' b0;
Bps_start <= 1 ' b0;
Tx_en <= 1 ' b0;
End

4 ' B0010:begin
Rd_fifo_req <= 1 ' b0;
Tx_data <= Wr_fifo_data;
State <= 4 ' b1000;
End

4 ' b1000:if (num==4 ' D10)
Begin
Bps_start <= 1 ' b0;
Tx_en <= 1 ' b0;
State <= 4 ' b0001;
End
Else
Begin
Bps_start <= 1 ' B1;
Tx_en <= 1 ' B1;
State <= 4 ' b1000;
End
Default:;
Endcase
End

Reg Rs232_tx_r;

Always @ (Posedge CLK or Negedge rst_n)
Begin
if (!rst_n)
begin
Num <= 4 ' D0;
Rs232_tx_r <= 1 ' B1;
End

Else if (tx_en)
Begin
If ((clk_bps_reg0 = = 1 ' b0) && (clk_bps = = 1 ' b1))//clk_bps clock along from low to high instantaneous
Begin
Num <= num+1 ' B1;
Case (NUM)
4 ' d0:rs232_tx_r <= 1 ' b0;//??????? λ
4 ' d1:rs232_tx_r <= tx_data[0];//???? Bit0
4 ' d2:rs232_tx_r <= tx_data[1];//???? Bit1
4 ' d3:rs232_tx_r <= tx_data[2];//???? Bit2
4 ' d4:rs232_tx_r <= tx_data[3];//???? BIT3
4 ' d5:rs232_tx_r <= tx_data[4];//???? BIT4
4 ' d6:rs232_tx_r <= tx_data[5];//???? BIT5
4 ' d7:rs232_tx_r <= tx_data[6];//???? BIT6
4 ' d8:rs232_tx_r <= tx_data[7];//???? BIT7
4 ' d9:rs232_tx_r <= 1 ' b1;//??????? λ
//4 ' D10:begin if (en_1==1) num<=0;else num<=10;end
Default:rs232_tx_r <= 1 ' B1;
Endcase
End
Else if (num==4 ' D10) num <= 4 ' d0;
//4 ' D10:if (en_1==1) num<=0;else num<=10;end

End
End

Assign rs232_tx = Rs232_tx_r;

Endmodule

Working serial communication