Write your own first phase of the processor (2) evolution of the--mips instruction set architecture

I will upload my new book, "Write My Own processor" (not yet published), today is the third article. I try four articles a week.

MIPS instruction set architecture since the advent of the 80 's. has been upgrading, from the initial MIPS I to MIPS V, to support the expansion module MIPS32, MIPS64 series, and integrated code compression technology microMIPS32, microMIPS64. Each MIPS Isa is a superset of its previous, no matter what omission, just add new features.

1, Mipsⅰ

Provides loading/storage, calculations, jumps, branching, co-processing, and other special instructions. The instruction set schema is used for the original MIPS processor r2000/r3000. The R2000 is the first MIPS CPU introduced in 1985, consisting of 110,000 transistors and is a 8MHz 32-bit processor. R3000 is the next-generation product of R2000. Compared to the former, however, the clock frequency is different.

2, Mipsⅱ

Added self-trapping instruction, link loading instruction, conditional store instruction, synchronization instruction, possible branch instruction, square root instruction. Originally planned for the MIPS processor R6000, but because of the problem of process selection, R6000 from 1988 began to design, has been the problem continues, finally failed to mass production.

But the Mipsⅱ instruction set architecture is a direct pioneer of the post-MIPS32 instruction set architecture.

3, Mipsⅲ

A 32-bit instruction set is provided, and a 64-bit instruction set is supported at the same time. Originally used for MIPS processor R4000. The R4000 is a 64-bit processor introduced in 1991, the first time the floating-point processor unit was added and the main clock frequency increased to 100MHz. A series of R4000 processors appeared later.

4, Mipsⅳ

The conditional move instruction, prefetch instruction and some floating point instructions are added on the basis of MIPS III. Originally used for MIPS processor R8000, later applied to r5000/r10000. R5000 and R10000 Although the same instruction set schema is used. But the design philosophy of the two architectures is completely different.

R5000 was launched in 1995. The use of the classic five-stage pipeline, sequential operation.

R10000 was launched in 1996 and is run in a disorderly sequence.

5, Mipsⅴ

On the basis of MIPS IV, the instructions to improve the efficiency of code production and data transfer are added. But no matter what a processor is based on that schema. The MIPS v instruction set architecture is a direct pioneer of the late MIPS64 instruction set architecture.

6, MIPS32/64

MIPS32/64 in 1998, MIPS32, based on MIPS II architecture, selectively added MIPS III, MIPS IV, MIPS V to improve the efficiency of code generation and data movement.

The MIPS64 is based on the MIPS V Architecture and is compatible with MIPS32 at the same time.

For the first time, the architecture includes the "CPU control" feature known as Coprocessor 0. Most MIPS processors designed since 1999 are compatible with this standard. 2003. Released the second edition of the MIPS32/64 Instruction set architecture (Release 2), also known as MIPS32/64 R2.

The latest is the fifth edition (Release 5). Also known as MIPS32/64 R5.

But the second edition is widely used now. The successful MIPS 4K, 24K series processors follow the MIPS32 R2 architecture.

MIPS32/64 also provides some application-specific instructions based on the basic instructions. These directives are in the form of a specific application extension (ase:application-specificextensions).

Whether a processor implements some kind of extension. Can be specified by setting the standard configuration register. The basic extensions are enumerated for example below.

• MIPS 16e: Designed for embedded systems and limited storage space applications, the ability to run 16-bit and 32-bit mixed-length instructions in a single program, can finally reduce the code length by 40%. MIPS32, MIPS64 all support MIPS 16e.
• Smartmips: Designed to meet the market needs of smart cards and flexible small systems. is an extended instruction set that efficiently saves storage space and also improves the performance of cryptographic operations that are critical to the smart card domain. MIPS32 supports Smartmips.
• Mips-3d: Provides better geometry processing, a pair of single-precision data types, and a dedicated instruction to speed up the processing of this type of data. MIPS64 supports Mips-3d, MIPS32 Second Edition also supports mips-3d.

• The Mcu:micro-control unit micro-control unit enhances memory-mapped I/O processing and provides lower interrupt latency. MIPS32, MIPS64 all support MCU.

7, MICROMIPS32/64

The MICROMIPS32/64 instruction set architecture integrates high-performance code compression technology with 16-bit and 32-bit optimization instructions, maintaining 98% MIPS32 performance, reducing the cost of the chip and reducing system power consumption at the same time by decreasing the code volume by at least 30%. The MIPS m14k kernel is the first MIPS32 compliant kernel to follow the micromips instruction set architecture published by MIPS Technology in 2009.

The evolution of the MIPS instruction set architecture can be described using figure 1-3. Note that there is no release 4 in the figure, which is due to very many people. 4 is an unlucky number. Therefore, MIPS did not publish release 4, but directly released release 5.

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Continue tomorrow!

Write your own first phase of the processor (2) evolution of the--mips instruction set architecture