X01. OS. 6: 8086 command

M: Memory
A: Accumulators
R: Register
Segr: segment register
Imm: immediate count
X: the flag bit status depends on the calculation or operation result.
U: the flag space is undefined.
-: No effect

Data transfer instruction clock count access times Byte Count affect flag meaning

MoV m, a 10 (14) 1 3-a --> m
MoV A, M 10 (14) 1 3-M -->
MoV R1, R2 2-2-R2 --> r1
MoV R, M 8 (12) + EA 1 2-4-M --> r
MoV M, r 9 (3) + EA 1 2-4-r --> m
MoV R, Imm 4-2-3-Imm --> r
MoV M, Imm 10 (14) + EA 1 3-6-Imm --> m
MoV segr, R16 2-2-R16 --> segr
MoV segr, M 8 (12) + EA 1 2-4-M --> segr
MoV R16, segr 2-2-segr --> R16
MoV M, segr 9 (13) + EA 1 2-4-segr --> m

Lea R16, M 2 + EA-2-4-offset m --> R16
LDS R16, M32 24 + EA 2 2-4-M32 segment address --> DS, M32 offset address --> R16
Les R16, M32 24 + EA 2 2-4-M32 segment address --> es, M32 offset address --> R16

Sahf 4-1 low 8-bit change ah --> flag low 8-bit
Lahf 4-1-flag low 8-> ah

Pop R 12 1 1-top stack --> r
Pop segr (CS illegal) 12 1 1-top stack --> segr
Pop m 25 + EA 2 2-4-top stack --> m
Popf 8 1 1 each flag changes the top of the stack --> flag

Pushf 10 1 1-flags into Stack
Push R 15 1 1-R into Stack
Push segr (CS illegal) 14 1 1-segr into Stack
Push M 24 + EA 2 2-4-M into Stack

Xchg A, R 3-1-A <--> r
Xchg R1, R2 4-2-R1 <--> r2
Xchg M, r 17 (25) + EA 2 2 2-4-M <--> r

Xlat source table 11 1 1-[bx + Al] --> Al

In Al, imm8 10 (14) 1 2-[imm8] --> Al
In ax, imm8 10 (14) 1 2-[imm8 + 1] [imm8] --> ax
In Al, DX 8 (12) 1 1-[dx] --> Al
In ax, DX 8 (12) 1 1-[dx + 1] [dx] --> ax

Out imm8, Al 10 (14) 1 2-Al --> [imm8]
Out imm8, ax 10 (14) 1 2-ax --> [imm8], [imm8 + 1]
Out dx, Al 8 (12) 1 1-Al --> DX
Out dx, ax 8 (12) 1 1-ax --> [-dx], [dx + 1]

Arithmetic operation instruction clock count access times Byte Count affect flag meaning
O d I t s Z A P C
Add R1, R2 3-2 x--x R1 + R2 --> r1
Add R, M 9 (13) + EA 1 2-4 x--x R + M --> r
Add R, Imm 4-3-4 x--x R + Imm --> r
Add a, Imm 4 1 2-3 x--x A + Imm -->
Add M, Imm 17 (25) + EA 2 3-6 x--x m + Imm --> m
Add M, R 16 (24) + EA 2 2-4 x--x m + r --> m

ADC R1, R2 3-2 x--x incoming bitwise addition: Destination operand + Source operand + carry flag
Adc r, M 9 (13) + EA 1 2-4 x--x --> destination operand
Adc r, Imm 4-3-4 x--x
Adc a, Imm 4-2-3 x--x
Adc m, Imm 17 (25) + EA 2 3-6 x--x
Adc m, R 16 (24) + EA 2 2-4 x--x

INC R8 3-2 x--x-R8 + 1 --> R8
INC R16 2-1 x--x-R16 + 1 --> R16
Inc m 15 (23) + EA 2 2-4 x--x-m + 1 --> m

AAA 4-1 U--u x adjust the sum of non-compressed BCD in Al
DAA 4-1 U---x adjust the sum of compressed BCD in Al

Sub R1, R2 3-2 x--x R1-R2 --> r1
Sub R, M 9 (13) + EA 1 2-4 x--x R-M --> r
Sub R, Imm 4-3-4 x--x R-IMM --> r
Sub A, Imm 4-2-3 x--x A-IMM -->
Sub M, Imm 17 (25) + EA 2 3-6 x--x M-IMM --> m
Sub M, R 16 (24) + EA 2 2-4 x--x M-R --> m

Sub R1, R2 3-2 x--x with bitwise subtraction: Destination-source-carry mark
Sub R, M 9 (13) + EA 1 2-4 x--x --> Objective
Sub R, Imm 4-3-4 x--x
Sub A, Imm 4-2-3 x--x
Sub M, Imm 17 (25) + EA 2 3-6 x--x
Sub M, R 16 (24) + EA 2 2-4 x--x

Dec R8 3-2 x---x-R8-1 --> R8
Dec R16 2-1 x---x-R16-1 --> R16
Dec M 15 (23) + EA 2 2-4 x--x-M-1 --> m

Neg R 2-2 x--x 0-r --> r
Neg M 16 (24) + EA 2 2-4 x--x 0-m --> m

CMP R1, R2 3-2 x--x R1-R2
Cmp r, M 9 (13) + EA-2-4 x--x R-M
Cmp r, Imm 4-3-4 x---x R-IMM
Cmp a, Imm 4-2-3 x--x A-IMM
Cmp m, Imm 10 (14) + EA-3-6 x--x M-IMM
Cmp m, r 9 (13) + EA-2-4 x--x M-R

AAS 4-1 U--u x adjusted the difference of non-compressed BCD in Al
Das 4-1 x---x adjust the compression BCD deviation in Al

Mul R8 70-77-2 x--u x Al * R8 --> ax
Mul R16 118-133-2 x---u x ax * R16 --> DX: ax
Mul M8 (76to83) + EA 1 2-4 x---u x Al * m --> ax
Mul M16 (128to164) + EA 1 2-4 x---u x ax * M16 --> DX: ax

Imul R8 80-98-2 x---u x except that the number of involved operations is an integer, it is the same as Mul.
Imul R16 128-154-2 x---u x
Imul M8 (86to104) + EA 1 2-4 x---u x
Imul M16 (138to164) + EA 1 2-4 x---u x

Amm 83-1 U---x u adjusted the non-compressed BCD product in ax

<-Div R8 80-90-2 U---u ax/R8 operator, remainder --> Al: Ah
<-Div R16 144-162-2 #: Same as DX: ax/R16 operator, remainder --> ax: DX
<-Div M8 (86to92) + EA 1 2-4 # Operator of ax/M8, remainder --> Al: Ah
<-Div M16 (154to172) + EA 1 2-4 # DX: Operator of ax/M16, remainder --> ax: DX

Idiv R8 101-112-2 #: the number of involved operations is a signed integer.
Idiv R16. 165-184-2 #
Idiv M8 (107to118) + EA 1 2-4 #
Idiv M16 (175to194) + EA 1 2-4 #

AAD 60-2 U---x u adjust the non-compressed BCD in ax to remove

CBW 2-1-if Al <80 h, Ah = 0, otherwise Ah = FFH
CWD 5-1-If AX <8000 h, dx = 0; otherwise dx = ffffh

Logical operation instruction clock count access times Byte Count affect flag meaning
O d I t s Z A P C
Not R 3-2 -! R --> r
Not M 16 (24) + EA 2 2-4 -! M --> m

Sal/shl r, 1 2-2 x---x u x [c] <-- [7 <---- 0] <-- 0
Sal/shl r, CL 8 + 4/bit-2 # arithmetic, logic shifts left once or CL bit
Sal/shl m, 1 15 (23) + EA 2 2 2-4 #
Sal/shl m, CL 20 (28) + EA + 4/bit 2 2-4 # + ---- +
|
Sar r, 1 2-2 0---x u x +-> [c] + --> | 7 | --> 0 | --- +
Sar r, CL 8 + 4/bit-2 # | _________________________ |
Sar m, 1 15 (23) + EA 2 2 2-4 # arithmetic shift 1 time or CL bit
Sar m, CL 20 (28) + EA + 4/bit 2 2-4 #

Shr r, 1 2-2 x--x u x +-> [c] 0-> [7 --> 0]-+
Shr r, CL 8 + 4/bit-2 # | _____________________ |
Shr m, 1 15 (23) + EA 2 2 2-4 # logic shifts one or CL bit to the right
Shr m, CL 20 (23) + EA + 4/bit 2 2-4 #

Rol R, 1 2-2 x---X [c] <-- + -- [7 <-- 0] <-+
Rol R, CL 8 + 4/bit-2 # | ___________ |
Rol M, 1 15 (23) + EA 2 2 2-4 # shift 1 or CL bit left without the carry Loop
Rol M, CL 20 (28) + EA + 4/bit 2 2-4 #

Ror R, 1 2-2 # [c]-+-> [7 --> 0]-+
Ror R, CL 8 + 4/bit-2 # | __________ |
Ror M, 1 15 (23) + EA 2 2 2-4 # shifts one or CL bits to the right of a loop without carry
Ror M, CL 20 (28) + EA + 4/bit 2 2-4 #

Rcl r, 1 2-2 # [c] <-- [7 <-- 0] <-- +
Rcl r, CL 8 + 4/bit-2 # | ______________ |
Rcl m, 1 15 (23) + EA 2 2 2-4 # shifts the round containing carry 1 or CL bit to the left
Rcl m, CL 20 (28) + EA + 4/bit 2 2-4 #

Rcr r, 1 2-2 # + --> [c] --> [7 --> 0]-+
Rcr r, CL 8 + 4/bit-2 # | _________________ |
Rcr m, 1 15 (23) + EA 2 2 2-4 # shifts one or CL bits to the right of a carry Loop
Rcr m, CL 20 (28) + EA + 4/bit 2 2-4 #

And R1, R2 3-2 0---x u x 0 R1 & R2 --> r1
And R, M 9 (13) + EA 1 2-4 # R & M --> r
And R, Imm 4-3-4 # R & Imm --> r
And a, Imm 4-2-3 # A & Imm -->
And M, Imm 17 (25) + EA 2 3-6 # M & Imm --> m
And M, R 16 (24) + EA 2 2-4 # M & R --> m

Test R1, R2 3-2 # R1 & r2
Test R, M 9 (13) + EA 1 2-4 # R & M
Test R, Imm 5-3-4 # R & IMM
Test A, Imm 4-2-3 # A & IMM
Test M, Imm 11 + EA-3-6 # M & IMM

Or R1, R2 3-2 # R1 | R2 --> r1
Or R, M 9 (13) + EA 1 2-4 # R | M --> r
Or R, Imm 4-3-4 # R | Imm --> r
Or a, Imm 4-2-3 # A | Imm -->
Or m, Imm 17 (25) + EA 2 3-6 # M | Imm --> m
Or m, R 16 (24) + EA 2 2-4 # M | r --> m

XOR R1, R2 3-2 # R1 ^ R2 --> r1
Xor r, M 9 (13) + EA 1 2-4 # R ^ m --> r
Xor r, Imm 4-3-4 # R ^ Imm --> r
Xor a, Imm 4-2-3 # A ^ Imm -->
Xor m, Imm 17 (25) + EA 2 3-6 # m ^ Imm --> m
Xor m, R 16 (24) + EA 2 2-4 # m ^ r --> m

Serial operation instruction clock count access times Byte Count affect flag meaning
O d I t s Z A P C
Movs target string, source string 18 (26) 2 1-source string --> Target string, modify source string address
Rep movs target string, source string 9 + 17 (25)/REP 2/Rep 1 -#

CMPS destination string, source string 22 (30) 2 1 X---x source string-destination string,
Rep CMPs target string, source string 9 + 22 (30)/REP 2/Rep 1 # (Si +-1)/(Si +-2), (di +-1) (di +-2)

SCAs destination string 15 (19) 1 1 # (Al-byte string)/(ax-string ),
Rep SCAs objective string 9 + 15 (19)/Rep 1/Rep 1 # (di +-1)/(di +-2)

Lods source string 12 (16) 1 1-source string --> Al/ax,
Rep lods source string 9 + 13 (17)/Rep 1/Rep 1-(Si +-1)/(Si +-2)

STOs objective string 11 (15) 1 1-Al --> byte string, ax --> string,
Rep STOs target string 9 + 10 (14)/Rep 1/Rep 1-(di +-1)/(di +-2)

Control Transfer Instruction clock count access times Byte Count affect flag meaning

Call near proc 19 (23) 1 3-the same below: directly or indirectly call the near-far process (or subroutine)
Call far proc 28 (36) 2 5-
Call M16 21 (29) + EA 2 2-4-
Call M32 37 (57) + EA 4 2-4-
Call R16 16 (24) 1 2-

JMP short number 15-2-the same below: unconditionally redirects to the position indicated by the operand to obtain the command
JMP near-label 15-3-
JMP far-label 15-5-
JMP M16 18 + EA-2-4-
JMP M32 24 + EA-2-4-
JMP R16 11-2-

RET 20 1 1-the same below: process, subroutine return. Segment, no operand
RET 24 1 3-
RET 32 2 1-
RET 31 2 3-

JB/jnae/JC short label 16/4-2-less than/not higher than or equal to/has an increment (when the bid is used), turn to the label line command
Jae/JNB/JNC short label 16/4-2-greater than or equal to/not lower than/without carry (when the digit is used), turn to the label line command

Je/JZ short label 16/4-2-equal to/When the result is 0, turn to the label line command
JNE/jnz short label 16/4-2-not equal to/When the result is not 0, turn to the label line command

When the JS short label 16/4-2-symbol mark SF is 1, turn to the short label line command
When the JNS short label 16/4-2-symbol flag SF is 0, turn to the short label line command

When the jp/jpe short label 16/4-2-parity mark PF is 1, the redirection label line command
Jnp/JPO short label 16/4-2-when the parity mark PF is 0, the redirection label line command

Jo short label 16/4-2-overflow, turning to label line command
Jno 16/4-2-No overflow, turning to the label line command

Ja/jnbe short label 16/4-2-greater than/not lower than, turn to label line command
When jbe/JNA short label 16/4-2-is less than or equal to/not higher than, turn to the label line command

Transfer when the JG/jnle short label 16/4-2-is greater than/not less than or equal
Transfer when jge/JNL short label 16/4-2-is greater than or equal to/not less
Jl/jnge short label 16/4-2-less than/not greater than or equal to, transfer
Transfer when jle/jng short label 16/4-2-is less than or equal to/not equal
When the jcxz short number is 18/6-2-cx = 0, the instruction indicated by the steering label

Loop short label 17/5-2-first CX-1, if CX! = 0, then the cycle is to the Command indicated by the label
Loope/loopz short label 18/6-2-first CX-1, if CX! = 0, and ZF = 1, turn to the label line command
Loopne/loopnz short label 19/5-2-first CX-1, if CX! = 0, and ZF = 0, turn to the label line command

O d I t s Z A P C
Int imm8 (Interrupt number = 3) 52 (72) 5 1--0 0---flag, Cs, IP into the stack, the corresponding interrupt vector of low words
Int imm8 (Interrupt number! = 3) 51 (71) 5 2 # send IP address, send CS

Into 53 (73)/4 5 1 # overflow, flag, Cs, IP are added to the stack, and the interrupt vector is low
Send IP address, send Cs with high-text, and execute in sequence without Overflow

Iret 32 (44) 3 1 x interrupt return, send three consecutive words at the top of the stack to the stack
IP, Cs, flag

Processor Control Instruction clock count access times Byte Count instruction meaning impact on flag bit

CLS 2-1 mark cf = 0 The Same below: Except for the operation of the specified mark, no effect on other marks
CMC 2-1 reversed the mark cf
STC 2-1 make cf = 1
CLD 2-1 to mark df = 0
STD 2-1 make df = 1
CLI 2-1 enable flag if = 0
STI 2-1 make if = 1

Hlt 2-1 enables the CPU to be suspended, and the external interrupt and reset signal can be enabled

Esc imm, M 8 (12) + EA 2-4 2-4 The master processor is not assigned to the coprocessor
Esc imm, R 2 2 2 # None

Wait 3 + 5N-1 wait until test becomes valid

NOP 3-1 null operation, only IP + 1 none

Lock any command 2-1 as any command bus block prefix none

Rep string operation command 2-1 CX! = 0, unconditionally repeat the subsequent instructions until the CX-1 = 0 No
Repe/repz string operation command 2-1 ZF = 1 and CX! = 0, repeat the subsequent command until the CX-1 is = 0 or ZF = 0 none
Repne/repnz string operation command # ZF = 0 and CX! = 0, repeat the subsequent command and CX-1 until CX-1 = 0 or ZF = 1 none

 

X01. OS. 6: 8086 command