X86 and arm virtual address translation. What is MMU and MMU?

I. What is the role of MMU?
MMU is short for memory management unit. For various CPUs, MMU is an optional accessory. MMU is responsible for converting physical addresses of virtual addresses and providing hardware-based Memory Access authorization.
In modern multi-user multi-process operating systems, MMU is required to achieve the goal that each user process has its own independent address space. when MMU is used, the OS divides an address area. In this address area, the content of each process is not necessarily the same. for example, in Microsoft Windows, the address is divided into 4-2 GB user address space. process a maps the executable file to the address 0x400000. process B maps the executable file to the address 0x400000. if the read address of process a is 0x400000, the executable file of process a is mapped to ram. when process B reads address 0x400000, it reads the executable file mapped to ram of process B.
This is the role of MMU in address translation.
Ii. MMU of X86 Series
MMU is integrated into Intel's 80 Gbit/s CPU or updated CPU to provide 32bit 4 GB address space.

Iii. Arm series MMU
The CPU produced by arm. MMU exists as a coprocessor. different series have different combinations. you need to query datasheet to see if MMU exists. if so, it must be a coprocessor numbered 15. A 32-bit 4G address space is provided.

IV addressing mode after MMU is started on x86
1. x86 MMU provides a 4 K/2 m/4 m page mode (depending on the CPU, provide different capabilities ), this section describes the 4 K page mode currently used by most operating systems. and does not provide access check. (after all, it is not a complete CPU manual .)
2. involved registers
A) gdt
B) LDT
C) Cr0
D) 303.
E) segment register
3. Steps for converting virtual addresses to physical addresses (Intel's 2 m/4 m page may be described in future articles)
A) segment register is used as the index of gdt or LDT to retrieve the corresponding gdt/LDT entry. note: Segment cannot be canceled, even in flat mode. it is wrong to disable segment register in flat mode. any Ram addressing command has the default segment assumption. the default segment is used unless the segment override prefix is used to change the segment of the current addressing instruction.
I. entry format
Typedef struct
{
Uint16 limit_0_15;
Uint16 base_0_15;
Uint8 base_16_23;

Uint8 accessed: 1;
Uint8 readable: 1;
Uint8 conforming: 1;
Uint8 code_data: 1;
Uint8 app_system: 1;
Uint8 DPL: 2;
Uint8 present: 1;

Uint8 limit_16_19: 4;
Uint8 unused: 1;
Uint8 always_0: 1;
Uint8 seg_16_32: 1;
Uint8 granularity: 1;

Uint8 base_24_31;
} Code_seg_descriptor, * pcode_seg_descriptor;

Typedef struct
{
Uint16 limit_0_15;
Uint16 base_0_15;
Uint8 base_16_23;

Uint8 accessed: 1;
Uint8 writeable: 1;
Uint8 expanddown: 1;
Uint8 code_data: 1;
Uint8 app_system: 1;
Uint8 DPL: 2;
Uint8 present: 1;

Uint8 limit_16_19: 4;
Uint8 unused: 1;
Uint8 always_0: 1;
Uint8 seg_16_32: 1;
Uint8 granularity: 1;

Uint8 base_24_31;
} Data_seg_descriptor, * pdata_seg_descriptor;

There are four entry formats. Here, the entry formats of code segment and data segment are provided. in flat mode, the entry is 0 at base_0_15, base_16_23, and 0xfffff at limit_0_15 and limit_16_19. granularity is 1. the table name segment address space is a 4G address space from 0 to 0xffffffff.
B) obtain the base address and limit from the segment. The address to be accessed is checked first to see if it exceeds the segment limit.
C) The address + base address to be accessed to form a virtual address that requires 32-bit access. The address is interpreted as follows:
Typedef struct
{
Uint32 offset: 12;
Uint32 page_index: 10;
Uint32 pdbr_index: 10;
} Va, * lpva;
D) pdbr_index is used as the index of F3. a data structure defined below is obtained.
Typedef struct
{
Uint8 present: 1;
Uint8 writable: 1;
Uint8 Supervisor: 1;
Uint8 writethrough: 1;
Uint8 cachedisable: 1;
Uint8 accessed: 1;
Uint8 reserved1: 1;
Uint8 pagesize: 1;

Uint8 ignoreed: 1;
Uint8 AVL: 3;
Uint8 ptadr_12_15: 4;

Uint16 ptadr_16_31;
} PVDF, * lppdde;
E) retrieve the address of the page table from the table and use page_index as the index to obtain the following data structure:
Typedef struct
{
Uint8 present: 1;
Uint8 writable: 1;
Uint8 Supervisor: 1;
Uint8 writethrough: 1;
Uint8 cachedisable: 1;
Uint8 accessed: 1;
Uint8 dirty: 1;
Uint8 PTA: 1;

Uint8 Global: 1;
Uint8 AVL: 3;
Uint8 ptadr_12_15: 4;

Uint16 ptadr_16_31;
} PTE, * lppte;
F) Obtain base address of the real physical address of the page from the Pte. The base address table name is physical address. The height is 20 bits. the offset of the virtual address is the physical address.

Addressing Mode after arm starts MMU
1. the paging mode provided by arm MMU is 1 K/4 K/64 K. this article describes the 4 K mode currently used by operating systems. and does not provide access check. (after all, it is not a complete CPU manual .)
2. All involved registers are in the coprocessor 15.
3. Arm has no segment register and is a real flat-mode CPU. Given an address, this address can be understood as the following data structure:
Typedef struct
{
Uint32 offset: 12;
Uint32 page_index: 8;
Uint32 pdbr_index: 12;
} Va, * lpva;
4. Fetch BIT14-31 from MMU register 2. pdbr_index is the index of this table. Each entry is 4 byte size. The structure is
Typedef struct
{
Uint32 type: 2; // always set to 01b
Uint32 writebackcacheable: 1;
Uint32 writethroughcacheable: 1;
Uint32 ignore: 1; // set to 1B always
Uint32 domain: 4;
Uint32 Reserved: 1; // set 0
Uint32 base_addr: 22;
} PVDF, * lppdde;
5. Obtain the PDE address, obtain the array in the following structure, and use page_index as the index to retrieve the content.
Typedef struct
{
Uint32 type: 2; // always set to 11b
Uint32 ignore: 3; // set to 100b always
Uint32 domain: 4;
Uint32 Reserved: 3; // set 0
Uint32 base_addr: 20;
} PTE, * lppte;
6. The base address and top offset obtained from the PTE constitute a physical address.
7. other bits in the PVDF/PTE are used for access control. What we talk about here is that everything is normal and the physical addresses are normally combined.

Differences in ARM/x86 MMU usage
1. x86 always has the segment concept, while arm does not (there is no segment register .).
2. arm has a domain concept. It is used for Access authorization. This is a concept not available in x86. When a general-purpose OS tries to apply to the CPU of both, domain usage is generally discarded.