X86 paging mechanism and corresponding System Structure

X86 paging mechanism and corresponding System Structure
The linear address space of 32bits can be directly mapped to the physical address space, or indirectly mapped to many small physical spaces (disk storage space. This indirect ing method is paging. The available page size for x86 is 4 kb, 2 MB, and 4 MB (2 MB and 4 MB can only be used in the Pentium and Pentium Pro processors, which is limited to 4 kb in this article ).
In the paging mechanism, x86 uses four data structures:
· Page Directory Entry: 32bits structure. A height of 20 bits indicates the base address (physical address) of the page table, in increments of 4 kb, and a low value of 12 bits indicates the page table attribute, for details about the conversion, refer to the subsequent initialization section;
· Page Directory: stores page Directory items on one page, which can contain a total of 1024 page Directory items;
· Page table item (PTE, page table entry): 32bits structure. A height of 20 bits indicates the base page address (physical address), and a low of 12 bits indicates the page attribute;
· Page table: stores page table items on one page, which can contain 1024 page table items in total;
· Page: 4 kb continuous address space;
To implement paging and improve address translation efficiency, x86 provides and uses the following hardware structure:
· Page flag (PG, page): this flag is 1, which indicates that the page mechanism is used. Actually, it is the 31bit of the control register Cr0;
· Page Cache/quick table (tlbs, translation lookaside buffers): stores recently used pdns and Pte to improve address conversion efficiency;
· Page Directory base address register (pdbr, page Directory base register): used to store the base address (physical address) of the page Directory. Actually, it is the control register F3;
To map linear addresses to physical addresses, x86 interprets the 32bits linear addresses as three parts: the 31bit to 22bit is the offset in the page Directory, used to index the page Directory items (get the base address of the corresponding page table); the offset from 21bit to 12bit is used to index the page table items (get the base address of the corresponding page ); the offset from 11bit to 0bit is the page offset. In this way, the physical address corresponding to the linear address can be correctly obtained through the offset between the two-level index and the page.