Zedboard How to control DDR read/write from PL end (ii)--axi bus

Although Xilinx has encapsulated the details of the Axi timing and given the official IP and wizard-generated custom IPs, the user only has to focus on their own logic implementation, but it is still necessary to understand the timing of Axi, after all, we do hardware design.

AXI (Advanced extensible Interface) is a bus protocol that is proposed by arm for the AMBA microcontroller bus Architecture) The most important part of the 3.0 protocol is an on-chip bus for high performance, high bandwidth, and low latency. Its address/control and data phase are separated, supporting misaligned data transfer, while in burst transmission, only the first address is required, while separating the read and write data channels, and supporting significant transmission access and disorderly access, and more easily on the line timing closure. AXI is a new high-performance protocol in Amba. AXI Technology enriches existing AMBA standard content to meet the demands of ultra-high performance and complex on-chip system (SoC) designs.

The Axi bus is a burst-based transmission bus that is divided into 5 channels: Read address, read data, write address, write data, write response.

• The read data channel is a transfer from slave to master, and in a read operation, the response is the same channel as read data, transfer returns response　　

　　

• The Write data channel is a transfer from master to slave, in which a whole response is returned in a write operation.

　　

• Each channel in Axi contains an information signal and a two-way vald, ready handshake mechanism. The information source uses the valid signal to indicate when the data and control information in the channel is valid. The source uses the ready signal to indicate when data can be received. Both the read data and the Write data channel include a last signal, which indicates the final data for the transfer of a thing.
• The Write data path transmits the write data of the host to the device. Each of the eight data will have a byte lane, which indicates which byte on the bus is valid. A write response channel provides a way for a device to respond to a write transaction. This completes the signal every burst read-write will produce one.
• The interface and interconnection diagram of the host and the device are as follows:

• Transport address information and data are valid when both valid and ready are high.
• The timing diagram for burst reading is as follows:

When the address appears in address bus, the transmitted data will appear on the read Data channel. The device remains valid low until the read data is valid. To indicate the completion of a burst read/write, the device uses a rlast signal to represent the last transmitted data.

• The overlapping burst read sequence diagram is as follows:

The device will process the second burst read data after the first burst reading is completed. It also means that the host first transmits two addresses to the device. The device begins processing data for the second address after it has completely processed the data for the first address.

• The burst write sequence diagram is as follows:

　　

At the beginning of this process, the host sends the address and control information to the write address channel, and then the host sends each write data to the write data channel. When the host sends the last data, the wlast signal becomes high. When the device has finished receiving all the data, he sends a write response back to the host to indicate that the write transaction is complete.

• The AXI protocol supports random-order transmissions. He gives every transaction through the interface a idtag. protocol requires the same ID tag transaction must be completed in an orderly manner, and the different ID tag can be completed in random order.

Signal Description:

1. Global Signal

Signal	Source	Describe
Aclk	Clock Source	Global Clock signal
Aresetn	Reset Source	Global reset signal, low active

2. Write Address channel Signal

Signal	Source	Describe
AWID[3:0]	Host	Write address ID, this signal is the ID tag of the write address signal group.
AWADDR[31:0]	Host	Write the address.
AWLEN[3:0]	Host	The length of the burst write. This length determines the number of data transmitted by the burst write.
AWSIZE[2:0]	Host	The size of the burst write.
AWBURST[1:0]	Host	The type of burst write.
AWLOCK[1:0]	Host	The lock type.
AWCACHE[3:0]	Host	The cache type. This signal indicates the bufferable, cacheable, Write-through, write-back, allocate attributes information for the transaction.
AWPROT[2:0]	Host	The type of protection.
Awvalid	Host	The write address is valid. 1 = address and control information valid 0 = Invalid address and control information This signal will remain until the awready becomes high.
Awready	Equipment	Write the address ready. This signal is used to indicate that the device is ready to accept address and control information. 1 = device Ready 0 = Device Not ready

3. Write Data channel signal

Signal	Source	Describe
WID[3:0]	Host	The value of the write ID Tag,wid must match the value of Awid
WDATA[31:0]	Host	Write the data.
WSTRB[3:0]	Host	Write the valve. Wstrb[n] marked interval is wdata[(8*n) +7: (8*n)]
Wlast	Host	Write the last data.
Wvalid	Host	Write valid 1 = Write data and valve valid 0 = Invalid write data and valve
Wready	Equipment	Write ready. Indicates that the device is ready to accept the data. 1 = device Ready 0 = Device Not ready

4. Write Response channel Signal

Signal	Source	Describe
BID[3:0]	Equipment	The response ID, which must match the value of Awid.
BRESP[1:0]	Equipment	Write Response. This signal indicates the state of the write transaction. Possible responses: OKAY, Exokay, Slverr, Decerr.
Bvalid	Equipment	Write response is valid. 1 = Write response is valid 0 = Invalid Write response
Bready	Host	Accept the response is ready. This signal indicates that the host has been able to accept the response information. 1 = host Ready 0 = Host Not ready

5. Read Address Channel Signal

Signal	Source	Describe
ARID[3:0]	Host	Read the address ID.
ARADDR[31:0]	Host	Read address.
ARLEN[3:0]	Host	Burst read-length.
ARSIZE[2:0]	Host	Burst-Read size.
ARBURST[1:0]	Host	Burst read type.
ARLOCK[1:0]	Host	The lock type.
ARCACHE[3:0]	Host	The cache type.
ARPROT[2:0]	Host	The type of protection.
Arvalid	Host	The read address is valid. The signal remains until the arready is high. 1 = address and control information valid 0 = Invalid address and control information
Arready	Equipment	The read address is ready. Indicates that the device is ready to accept the data. 1 = device Ready 0 = Device Not ready

6. Read Data channel signal

Signal	Source	Describe
RID[3:0]	Equipment	Read ID tag. The value of the RID must match the value of arid.
RDATA[31:0]	Equipment	Read the data.
RRESP[1:0]	Equipment	Read response. This signal indicates the state of the read transmission: OKAY, Exokay, Slverr, Decerr.
Rlast	Equipment	Read the last data that the transaction is transmitting.
Rvalid	Equipment	Read data is valid. 1 = read Data valid. 0 = Invalid read data.
Rready	Host	Read data ready. 1 = host Ready 0 = Host Not ready

7. Low Power Interface Signal

signal	source
csysreq	< P align= "left" >clock controller	system low Power request. This signal comes from the system clock controller, allowing the peripheral device to enter a low-power state.
csysack	< P align= "left" > peripherals	low power request response.
cactive	< P align= "left" > peripherals	clock active 1 = Peripheral Clock Request 0 = peripheral clock No request

Zedboard How to control DDR read-write from PL end (ii)--axi bus