Zynq in-chip XADC Application Note

Zynq in-chip XADC Application Note

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Application Note briefly describes the resources and several applications of Xilinx Zynq XADC. Reference Documentation:

U ug480:7series_xadc.pdf;

U xapp795:driving-xadc.pdf

U xapp554:xadc-layout-guidelines.pdf

U xapp1203:post-proc-ip-zynq-xadc.pdf

U xapp1183:zynq-xadc-axi.pdf

U xapp1182:zynq_axi_xadc_mon.pdf

U xapp1172:zynq_ps_xadc.pdf

U pg019:axi_xadc.pdf

U pg091:xadc-wiz.pdf

U ug953:vivado-7series-libraries.pdf

U ug585:zynq-7000-trm.pdf

1 XADC Overview

The XADC is a 12bit 1MSPS in the central position of the ZYNQ series device Pakage, with a built-in temperature sensor that can monitor the on-chip junction temperature, each voltage data and the output alarm signal in real time. Figure 1 is the XADC primitive structure.

Figure 1 XADC Primitive structure

As can be seen from Figure 1, the XADC analog input includes a dedicated analog input VP/VN and 16 groups of multiplexed analog signal input Vaux (15:0), XADC conversion results can be output via a dynamic reconfiguration interface (DRP) or JTAG interface, the alarm signal can be output through ALM (7:0), And there is a dedicated temperature warning signal ot.

Thus, the final way to control XADC and obtain the resulting data is necessarily through the DRP or JTAG interface, regardless of what interface is encapsulated outside it, but eventually converted to a DRP or JTAG implementation and XADC directly connected.

The Application note only discusses the control of XADC and the contents of the read results programming, see the following:

① User manual: UG480;

② front-end analog drive circuit design: xapp795;

③PCB layout design: xapp554.

2 XADC Access

XADC Access Path structure 2, the user can access XADC through the Pl-jtag, PS-XADC, and AXI-GP master interfaces, the first two in the PL logic without invoking the XADC primitive can be accessed directly, the latter need to call the XADC IP core.

Figure 2 XADC Interconnect path map

2,PS-XADC sends the DRP command serially to the XADC module, which is selected with Pl-jtag Two and is devcfg through the register bit. XADCIF_CFG[31] To select, the DRP interface is always valid.

2.1 Access via Pl-jtag

This is the system default and can be obtained directly in Vivado's hardware manager with a temperature-voltage curve, etc., as shown in 3.

Figure 3 Tool reading XADC drawing curve interface

2.2 Access via PS-XADC

DEVCFG.XADCIF_CFG[31] is selected by PS-XADC Access first to select the PS-XADC path, so that the DRP address and data for "command Register" will be written to "devcfg" according to the specified command format. Xadcif_cmd_fifo "read the data by reading" Devcfg. Xadcif_rdfifo ", low 16bit is the value of the DRP register. See the description of gu585 "30.3 PS-XADC interfacedescription" in more detail.

For this access, Xilinx provides a complete SDK package, Linux drivers, and a GUI graphical interface based on webserver.

①SDK Package Resource (2015.2): in.. /sdk/2015.2\data\embeddedsw

\xilinxprocessoriplib\drivers\xadcps_v2_2 the path;

②linux driver and webserver GUI See application documentation XAPP1172.

2.3 Access via AXI-GP Master

This access is actually to replace the Axi interface with the DRP interface to access XADC, the need to call the logical IP Xadc_wiz,vivado 2015.2 version is V1.0, the user manual and datasheet see the official Xilinx documentation:

①pg091:xadc-wiz.pdf;

②pg019:axi_xadc.pdf.

Access to Xilinx via the Axi interface two models are available, one of which is the data and commands are read through the same AXI_GP interface, and the control command is issued via the Axi interface, and the data is DMA directly to the DDR via the Axi stream interface.

2.3.1 data and commands via the same Axi interface

This implementation of Xilinx provides the official reference Application XAPP1182, implemented by the system architecture shown in 4.

Figure 4 Implementing the schema with the same Axi interface

The architecture sends instructions and obtains ad conversion results via the Axi GP interface and displays the webserver GUI results on the PC via a gigabit network.

For this access, Xilinx provides a complete SDK package, Linux drivers, and a GUI graphical interface based on webserver.

①SDK Package Resource (2015.2): in.. /sdk/2015.2\data\embeddedsw

\xilinxprocessoriplib\drivers\ sysmon_v7_1 Path;

②linux driver and webserver GUI See application documentation XAPP1182.

2.3.2 data and commands via different AXI interfaces

This implementation of Xilinx provides the official reference Application XAPP1183, implemented by the system architecture shown in 5.

Figure 5 Implementation architecture for different AXI interfaces

The architecture controls the XADC IP core via Axi GP0 master, axi DMA IP Core, etc., and the ad conversion results are written to the DDR via DMA through a series of arithmetic operations. The results of the final calculation are sent through the serial port to the "AMS101 evaluator GUI" display. The benefit of this connection is that you can do some column processing of the ad Transform data before writing to the DDR.

For this access, Xilinx provides a full Linux drive and GUI graphical interface based on built-in LabVIEW.

See document XAPP1183 for Linux driver and GUI applications.

2.4 On-chip sensor application Brief

This section describes the relationship between on-chip sensors and ad-loaded result codes and the considerations for key register settings.

2.4.1 on-chip sensor conversion relationship

The conversion correspondence between the on-chip temperature sensor and the voltage sensor is shown in table 1.

table 1 on-chip sensor results corresponding relationship

Sensor	Ad conversion Result Conversion	Note
Temperature sensor	T = (ADC Code * 503.975)/4096–273.15
Voltage Sensors	V = (ADC code/4096)

2.4.2 Auto Power off protection

The XADC has an automatic shutdown protection function, which must be used to:

① register enable: the low four bits of the OT upperalarm Register (53H) must be 0011b;

② set Thresholds: OT upperalarm Register (53H) and OT lower alarm register (57H);

③ Enable signal: Set the OT bit of configurationregister 1 (41H) to 0, or use constraints:

Set_property bitstream. CONFIG. Overtemppowerdown Enable [Current_design]

The principle of automatic power off protection is: when the temperature exceeds the high temperature gate, wait for 10ms to enter the shutdown sequence, and the Ghigh (see UG470) signal is high, when the temperature is lower than ot lower, ghigh low, while entering the start-up reconfiguration state, the system re-load restart.

When entering the high temperature protection state, the XADC automatically generates the clock using the internal crystal oscillator, but the other state does not change. To improve INL and SNR performance, you can use constraint statements to:

Set_property bitstream. General. Xadcenhancedlinearity on [Current_design]

3 Summary

Summing up the XADC of the three kinds of access, through the Pl-jtag interface can be directly on the development tool to get load-change results curve, debugging is very convenient, through the PS-XADC interface access, without any additional logical resources to directly get results, but relatively slow speed, It is suitable for the system to detect the low-speed data such as temperature and voltage, and to obtain higher access efficiency through Axi interface, and to add some column digital signal processing algorithm on the Axi interface output data side and then output the final result, we can get the optimal realization scheme.

Using the XADC also has the high temperature automatic shutdown protection function, can effectively protect the device to burn at high temperature.

Have any zynq design problems, welcome to join QQ Group: 3,001,486,441 to discuss.

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Zynq in-chip XADC Application Note