ZYNQ PS DMA Controller Application Note

ZYNQ PS DMA Application Note

Hello,panda

The DMA controller at the PS end of the ZYNQ-7000 series devices is implemented using ARM's IP core DMA-330 (PL-330). Refer to the ARM's official documentation for the hardware details of the DMA controller and the associated instruction set and programming example content:

DDI0424D:dma330_r1p2_trm.pdf

DAI0239A:dma330_example_programs.pdf

This development environment for the Xilinx SDK2015.2,DMA library version is dmaps_v2_1.

1 Structural features

The DMA controller has the following characteristics:

N 8 independent channels, 4 can be used for PL-PS data management, each channel has 1024Byte Mfifo;

n using cpu_2x clock handling data, cpu_2x = (CPU FRQ/6);

N Perform DMA commands within the custom memory area to run the DMA;

n AHB control register supports both secure and non-secure modes;

N 4-word cache per channel;

n can access the following mapped physical addresses of the SOC:

DDR, OCM, PL, Linear QSPI Read, SMC, and M_AXI_GP devices, access the device's interconnect structure as shown in 1.

Figure 1 Zynq access to the Interconnect structure diagram

Figure 1 shows that the DMA controller can access all devices connected to the central interconnect and provides a four-channel peripheral management interface that can be used to control the data handling of the pl.

The DMA controller in the ZYNQ series devices uses Arm PL-330 IP and R1P1, as shown in block Diagram 2.

Figure 2 ZYNQ DMA Controller structure diagram

As shown in 2, the DMA controller consists of the instruction acceleration engine, the Axi Master data interface, the Axi APB Register Access interface, and the peripheral request interface that can be connected to the PL, the data buffer FIFO and the control and status generation units.

As you can see from Figure 2, the DMA PL330 is designed to perform its own instructions through the DMA instruction execution engine and feed the execution state to the CPU via the APB bus and interrupts to achieve the purpose of data handling without CPU consumption.

The DMA controller has eight channels, four of which are responsible for data handling on the central Interconnectcun storage unit, and four data channels are peripheral request interfaces that can be used for data access management of the PL axi Interconnect interface.

Each DMA channel executes its own instructions and has its own independent thread, with no effect on the channel. The command execution engine has its own independent cache line.

2 programming model

This article does not consider the peripheral request interface, the DMA controller programming is divided into the following parts:

U DMA controller initialization;

U organization DMA engine Execution code;

U start or stop DMA transfer;

U exception handling.

2.1 DMA Controller Initialization

DMA controller initialization, DMA initialization includes configuration clock, reset, security status, interrupt service, etc., as shown in table 1 below.

Table 1 Dmac Initialization configuration

Steps	Configuration Items	Related registers	Describe
1	Configuring the Clock		Enable APB clock, generally already enabled
		SLCR. Aer_clk_ctrl [Dma_cpu_2xclkact]=1 ' B1	Enable cpu_2x clock to Axi
2	Configure security Status	SLCR. Tz_dma_ns = 1	Non-secure
		SLCR. Tz_dma_irq_ns=1	Non-secure
		SLCR. Tz_dma_periph_ns=1	Non-secure
3	Reset	SLCR. Dmac_rst_cltr[dmac_rst]	Reset Dmac
4	Interrupt		Set Interrupt Service function

The normal clock and reset are all done in FSBL, and the user only needs to set up the APB Bus security mode and interrupt service function of DMA. Special attention should be paid to the setting of Safe mode, otherwise there is no valid answer to access Safe mode registers in non-safe mode.

2.2 Organization DMA engine execution Code

The Xilinx SDK (GCC) does not support compiling DMA engine directives, so it is necessary to control the description of the instruction set in the arm's official document "Ddi0424d_dma330_r1p2_trm.pdf" with an organization directive, It is important to note that the length of the execution instruction should be an integer multiple of the cache line and insufficient for NOP.

The following is an example of the Dmamov instruction, which shows how to write the machine code executed by the instruction engine, and Figure 3 is the encoding of the Dmamov instruction.

Figure 3 Encoding of the Dmamov instruction

This instruction code is composed of 48 bits (6 bytes) and the encoding in 3:

①RD[2:0]: Represents the register address, 000 is the source address register sar,001 for the Channel control register Ccr,dar is the destination address register.

②IMM[31:0], the configuration value for the above three registers.

CCR for the Axi bus configuration register, see the description of the section 3.3.15 Channel Control registers in document DDI0424D; About AXI Bus Protocol interface Description Self-referencing ARM official documentation ihi 0022d:amba AXI Andace Protocol specification.

Then the function to generate the Dmamov machine code is as follows:

INLINE int Xdmaps_instr_dmamov(char *dmaprog,unsigned Rd, u32 Imm)

{

/*

* Dmamov Encoding

* 15 4 3 2 1 10 ... 8 7 6 5 4 3 2 1 0

* 0 0 00 0 | Rd [2:0]|1 0 1 1 1 1 0 0

*

* 47 ... 16

* IMM[32:0]

*

* Rd: b000 for SAR, b001 CCR, b010 DAR

*/

*dmaprog= 0xBC;

* (dmaprog+ 1) = Rd & 0x7;

Xdmaps_memcpy4 (dmaprog+ 2, (char *) &IMM);

return 6;

}

So, look at the following assembly code, code completion 160K data handling, data source and purpose are DDR:

Dmamov SAR #SrcAddr

Dmamov DAR #DstAddr

Dmamov CCR #CCRn

Dmalp Lc1 Outerloop

Dmalp lc0 Innerloop

Dmald

Dmast

Dmalpend lc0

Dmald

Dmast

Dmalpend Lc1

Dmasev

Dmaend

The DMAC provides two counters lc0 and Lc1, all 8bit, so the number of cycles per layer cannot exceed 256 times. When the instruction is executed to Dmasev, the controller issues a complete interrupt, and any errors or exceptions encountered during execution are Abrot interrupted.

in this example srcaddr=0x10000000,dstaddr = 0x11000000, the parameter with the data length 160KB,CCRN is as follows:

Ccrn.endianswapsize = 0x00;

Ccrn.Dstcachectrl =0x00;

Ccrn.Dstprotctrl = 0x00;

Ccrn.Dstburstlen = 0x07;

Ccrn.dstburstsize = 0x03;

Ccrn.dstinc =0x01;

Ccrn.Srccachectrl = 0x00;

Ccrn.Srcprotctrl = 0x00;

Ccrn.Srcburstlen = 0x07;

Ccrn.srcburstsize = 0x03;

Ccrn.srcinc =0x01;

Then the executable machine code generated by the library function Xdmaps_builddmaprog is:

[ADDR] Code

[0] BC

[1] 0

[2] 0

[3] 0

[4] 0

[5] 10

[6] BC

[7] 2

[8] 0

[9] 0

[A] 0

[B] 11

[C] BC

[D] 1

[E] 77

[F] C0

[Ten] 1D

[11] 0

[12] 22

[13] 9

[14] 20

[] FF

[16] 4

[17] 8

[18] 38

[19] 2

[1 A] 3C

[1 B] 6

[1C] 34

[1D] 0

[1E] 0

The SEV interrupt occurs after the code is properly executed, and the current interrupt state is cleared in the Interrupt service program.

2.3 Start or Stop DMA transfer

In many registers of the DMA controller, the vast majority only reflects the current execution of the DMA engine and is used to implement the tracking execution state. The critical registers dbgstatus, Dbgcmd, DBGINST0, DBGINST1 are used to control the start, interrupt, and termination of the DMA. In other words, Dmago, Dmasev, and Dmakill in the DMA instruction, because of the asynchronous relationship between the APB interface and the DMA engine, there is a certain delay in instruction execution, and it is important to check that the last instruction is executed by reading the value of the dbgstatus before issuing the next instruction.

2.4 Exception handling

When encountering a DMA Abrot interrupt event, a Dmakill instruction must be issued to terminate the current thread.

3 Summary

The ARM PL330 DMA controller appears to be difficult to understand at first glance, in fact it treats Dmac as a co-processor and has its own command execution engine. After the user organizes the execution machine code and then saves it to memory, the user sends out the Dmago instruction via the APB interface to tell dmac the instruction execution engine executes the code's first address and starts the DMA instruction engine until the instruction executes to dmaend stop.

Note: For example, if the SDK is installed in the D:\Vivado\SDK directory and the version is 2015.2, then the DMAC Reference sample code is stored in the D:\Vivado\SDK\2015.2\data\embeddedsw\

Xilinxprocessoriplib\drivers\dmaps_v2_1\examples "path.

Copyright NOTICE: This article for Bo Master original article, without Bo Master permission not reproduced.

ZYNQ PS DMA Controller Application Note